From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 05BB1C3065A for ; Thu, 17 Aug 2023 15:44:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353278AbjHQPno (ORCPT ); Thu, 17 Aug 2023 11:43:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59256 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1353291AbjHQPni (ORCPT ); Thu, 17 Aug 2023 11:43:38 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 07DBD30D8 for ; Thu, 17 Aug 2023 08:43:37 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 8DEA3674D2 for ; Thu, 17 Aug 2023 15:43:36 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id E0AA1C433C8; Thu, 17 Aug 2023 15:43:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1692287016; bh=ENSBmFTwAkmLWRSPDWXacvhCmkoWqWKBl83e4JjNB0g=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=Whf9CQf5w/JqP75xeV5sFKVekukqAQb4oKu36Ppo7n1Bpb+oWmc+2x+YYYhSrefbi jIaAF6dlggiE5szzkLNXzZASE4PSmupbZWZNYyywTf42ltabFnDWp/MXejy0CNS3In 2qdZL4OBKZQQhZfsJWzTXWf58FasP8Bz0GG/KDnvaqACMdVu+UWyz+DcnbRFYQzJd1 Cq+ggCibb73NqumzWvpRweyNf2OZ4SKPmOGJcdiDZmruOLhPzlKfZUxF74Nn/nKyu/ 9tGOqa9SA0SwR/bF80DfUyvMaU9DKAgaLnhneq6X9TaRxnMlUTl72GL69r/UdRpqyg OVy+zAZ3I4NxA== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1qWf9p-005izV-FM; Thu, 17 Aug 2023 16:43:33 +0100 Date: Thu, 17 Aug 2023 16:43:33 +0100 Message-ID: <86r0o1fzdm.wl-maz@kernel.org> From: Marc Zyngier To: Jing Zhang Cc: KVM , KVMARM , ARMLinux , Oliver Upton , Will Deacon , Paolo Bonzini , James Morse , Alexandru Elisei , Suzuki K Poulose , Fuad Tabba , Reiji Watanabe , Raghavendra Rao Ananta , Suraj Jitindar Singh , Cornelia Huck Subject: Re: [PATCH v8 05/11] KVM: arm64: Enable writable for ID_AA64DFR0_EL1 and ID_DFR0_EL1 In-Reply-To: <20230807162210.2528230-6-jingzhangos@google.com> References: <20230807162210.2528230-1-jingzhangos@google.com> <20230807162210.2528230-6-jingzhangos@google.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: jingzhangos@google.com, kvm@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, oliver.upton@linux.dev, will@kernel.org, pbonzini@redhat.com, james.morse@arm.com, alexandru.elisei@arm.com, suzuki.poulose@arm.com, tabba@google.com, reijiw@google.com, rananta@google.com, surajjs@amazon.com, cohuck@redhat.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On Mon, 07 Aug 2023 17:22:03 +0100, Jing Zhang wrote: > > All valid fields in ID_AA64DFR0_EL1 and ID_DFR0_EL1 are writable > from usrespace with this change. nit: userspace > > Signed-off-by: Jing Zhang > --- > arch/arm64/kvm/sys_regs.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c > index afade7186675..5f6c2be12e44 100644 > --- a/arch/arm64/kvm/sys_regs.c > +++ b/arch/arm64/kvm/sys_regs.c > @@ -2006,7 +2006,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { > .set_user = set_id_dfr0_el1, > .visibility = aa32_id_visibility, > .reset = read_sanitised_id_dfr0_el1, > - .val = ID_DFR0_EL1_PerfMon_MASK, }, > + .val = GENMASK(63, 0), }, For obvious reasons, this cannot be a 64 bit mask... > ID_HIDDEN(ID_AFR0_EL1), > AA32_ID_SANITISED(ID_MMFR0_EL1), > AA32_ID_SANITISED(ID_MMFR1_EL1), > @@ -2055,7 +2055,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { > .get_user = get_id_reg, > .set_user = set_id_aa64dfr0_el1, > .reset = read_sanitised_id_aa64dfr0_el1, > - .val = ID_AA64DFR0_EL1_PMUVer_MASK, }, > + .val = GENMASK(63, 0), }, What is the actual justification to go from "only the PMU version is writable" to "everything is writable"? Also, what about the RES0 fields? Thanks, M. -- Without deviation from the norm, progress is not possible.