From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 415FC349B07; Wed, 17 Dec 2025 17:13:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765991631; cv=none; b=E31cYBGdA3re4g2pwVI/FoReWSxfe4KvaqMzszQ4YEZ9Us+94kv8Rfc6C5D36g4R88X4OVHg0+x8tlYVI/L3KD5BSx5h3M3Bm5F4KxD2tbCt6dyP6p2Fxp6zcHexp2f+bqXq7ffml6q5G2oLpHSVePlg4yRcYe8DfhqypoYjXHQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765991631; c=relaxed/simple; bh=hP6aS6dR1CxDFuuYxfZTxYd+l+xS+uH+myfD+TNx5mg=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=dfxdU356A7n+Oybs057F+ZNnnnSPZldDYfexYUoioX+HVO2QMtwBp8fk7ooEqIrVu/U8yeBuThMA8442DA4p1nupaRASABMEcsM040gKLMTyw2umIc0UYMC21VuQYsyA8xUgJ7VkOxfqU/QgxkVnqIQtTc/AUjEa4bcZ2RoTd0Q= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=a58XlnQB; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="a58XlnQB" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D346EC4CEF5; Wed, 17 Dec 2025 17:13:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1765991630; bh=hP6aS6dR1CxDFuuYxfZTxYd+l+xS+uH+myfD+TNx5mg=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=a58XlnQB5gxYoKgEQXiEJRyLri+G4zKwum8Y4f5pEz+1OoHI+nzMxMPsb1eMLRL/k XMeeNWqKe/5/kABESM8eQh1eV064kUQz1gsyU8SIlPI/8HkRphsbFa2TfU/ekpuqjR 6v+aNs1Iajp4c6NEWQ6yeSUHPK7pGrYPrlRFMIk4HI+Z2ZaniFTchj1pzg54/LsXZo gFT5e3lSPRfQ/+5u8iGtY7GmUaK/b3xj0Jvv/ZH3h47aNdT8lRHnA/jadbUrMMJ8di FtJtOISys39iTsREWd82FBfcS9B4a2Q3FMy2gzegNHD4/IUov93W9GgER29Z7aorhp 4vYhRL+ZDIWmg== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1vVv5w-0000000DRqF-1tHd; Wed, 17 Dec 2025 17:13:48 +0000 Date: Wed, 17 Dec 2025 17:13:47 +0000 Message-ID: <86v7i5m3p0.wl-maz@kernel.org> From: Marc Zyngier To: Sascha Bischoff Cc: "linux-arm-kernel@lists.infradead.org" , "kvmarm@lists.linux.dev" , "kvm@vger.kernel.org" , nd , "oliver.upton@linux.dev" , Joey Gouly , Suzuki Poulose , "yuzenghui@huawei.com" , "peter.maydell@linaro.org" , "lpieralisi@kernel.org" , Timothy Hayes Subject: Re: [PATCH 19/32] KVM: arm64: gic-v5: Init Private IRQs (PPIs) for GICv5 In-Reply-To: <20251212152215.675767-20-sascha.bischoff@arm.com> References: <20251212152215.675767-1-sascha.bischoff@arm.com> <20251212152215.675767-20-sascha.bischoff@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: Sascha.Bischoff@arm.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, nd@arm.com, oliver.upton@linux.dev, Joey.Gouly@arm.com, Suzuki.Poulose@arm.com, yuzenghui@huawei.com, peter.maydell@linaro.org, lpieralisi@kernel.org, Timothy.Hayes@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Fri, 12 Dec 2025 15:22:41 +0000, Sascha Bischoff wrote: > > Initialise the private interrupts (PPIs, only) for GICv5. This means > that a GICv5-style intid is generated (which encodes the PPI type in > the top bits) instead of the 0-based index that is used for older > GICs. > > Additionally, set all of the GICv5 PPIs to use Level for the handling > mode, with the exception of the SW_PPI which uses Edge. This matches > the architecturally-defined set in the GICv5 specification (the CTIIRQ > handling mode is IMPDEF, so pick Level has been picked for that). > > Signed-off-by: Sascha Bischoff > --- > arch/arm64/kvm/vgic/vgic-init.c | 41 +++++++++++++++++++++++------- > include/linux/irqchip/arm-gic-v5.h | 2 ++ > 2 files changed, 34 insertions(+), 9 deletions(-) > > diff --git a/arch/arm64/kvm/vgic/vgic-init.c b/arch/arm64/kvm/vgic/vgic-init.c > index b246cb6eae71b..51f4443cebcef 100644 > --- a/arch/arm64/kvm/vgic/vgic-init.c > +++ b/arch/arm64/kvm/vgic/vgic-init.c > @@ -263,13 +263,19 @@ static int vgic_allocate_private_irqs_locked(struct kvm_vcpu *vcpu, u32 type) > { > struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; > int i; > + u32 num_private_irqs; > + > + if (vgic_is_v5(vcpu->kvm)) > + num_private_irqs = VGIC_V5_NR_PRIVATE_IRQS; > + else > + num_private_irqs = VGIC_NR_PRIVATE_IRQS; This is another case where we need to do something about PPIs. Allocating the full complement of PPIs (all 128 of them) is starting to be mildly visible (at 96 bytes a pop, that's 12kB of storage per vcpu). And 95% of that is guaranteed to be wasted... XArray anyone? > > lockdep_assert_held(&vcpu->kvm->arch.config_lock); It is good practice to leave this sort of assertions at the beginning of the function. Thanks, M. -- Without deviation from the norm, progress is not possible.