From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C7E0C1A8BEF; Wed, 31 Jul 2024 08:55:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722416131; cv=none; b=GQBUxSz889WwZBioOU3Otlcl8WTxB+LcO8v33fqQ2ThULNWetHiAe4dYTtJULxHEX60WyYG4u9Dv3M9WWtpMAAli52cJqgJWk/OIFGP00JIhUKahHSxYeOnGAhvaeROOaNnwZh9t/OSIswynG20lE0qdyOL2qtMwgN2VVwZeVFQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722416131; c=relaxed/simple; bh=1/obZN8eqhuQg8eIft5PGQVdNA3F7mgIIsdD8/S63mQ=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=EUEaEGWbC+6OUnxj/mDPbmWR7sOxcFlDqv+e5ST9hKVnVGWTXSXYoPxuIsaa/wGzJFE9Sb+S2kBhuDadBzxTgkDG8xsr1ADtaneyicS8viQ4A3nrSIFwcgKfarJKYaSLuauVGwp01WuTt0kZgcm5XxAl1Alg1H/4q9KHfQRd/lc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=MSTXZA2f; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="MSTXZA2f" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 127ABC4AF0C; Wed, 31 Jul 2024 08:55:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1722416131; bh=1/obZN8eqhuQg8eIft5PGQVdNA3F7mgIIsdD8/S63mQ=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=MSTXZA2fnA63cmsiN2ODSRPS1XC56eQdFCOdGllAcNyvxz0O0a97sm6/2v57AZBtq Cjo8cxtikdmP3xM67DNL7BbvRQ5dO7OvGjI16Sp1G5DVPvFJMAku3rkTet9WJrohrW qPAF/pG8ZaV4I1aWh4Y05d0yTxLkOUwIO2Stc2ed7/Q17nim+p7r8zdw1lOlXgTszn zWFTPiOna+9iSe/zmjeQQbgzixZ3FJrwoBf6NJ0OKHCcYAZn8uSa343zt09oFSIxQt q5ueDbHn1+fleKmaisw8ARcc/uJXR8vcAL0CEmW2WMtCqgnzRapTVOsd+qzEkXCZLb KdkZCIAmexMLw== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1sZ57I-00Gv7m-Dk; Wed, 31 Jul 2024 09:55:28 +0100 Date: Wed, 31 Jul 2024 09:55:28 +0100 Message-ID: <86v80m0wlb.wl-maz@kernel.org> From: Marc Zyngier To: Alexandru Elisei Cc: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, James Morse , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Joey Gouly Subject: Re: [PATCH 10/12] KVM: arm64: nv: Add SW walker for AT S1 emulation In-Reply-To: References: <20240625133508.259829-1-maz@kernel.org> <20240708165800.1220065-1-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.3 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: alexandru.elisei@arm.com, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, james.morse@arm.com, suzuki.poulose@arm.com, oliver.upton@linux.dev, yuzenghui@huawei.com, joey.gouly@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Mon, 29 Jul 2024 16:26:00 +0100, Alexandru Elisei wrote: > > Hi Marc, > > On Mon, Jul 08, 2024 at 05:57:58PM +0100, Marc Zyngier wrote: > > In order to plug the brokenness of our current AT implementation, > > we need a SW walker that is going to... err.. walk the S1 tables > > and tell us what it finds. > > > > Of course, it builds on top of our S2 walker, and share similar > > concepts. The beauty of it is that since it uses kvm_read_guest(), > > it is able to bring back pages that have been otherwise evicted. > > > > This is then plugged in the two AT S1 emulation functions as > > a "slow path" fallback. I'm not sure it is that slow, but hey. > > > > Signed-off-by: Marc Zyngier > > --- > > arch/arm64/kvm/at.c | 538 ++++++++++++++++++++++++++++++++++++++++++-- > > 1 file changed, 520 insertions(+), 18 deletions(-) > > > > diff --git a/arch/arm64/kvm/at.c b/arch/arm64/kvm/at.c > > index 71e3390b43b4c..8452273cbff6d 100644 > > --- a/arch/arm64/kvm/at.c > > +++ b/arch/arm64/kvm/at.c > > @@ -4,9 +4,305 @@ > > * Author: Jintack Lim > > */ > > > > +#include > > + > > +#include > > #include > > #include > > > > +struct s1_walk_info { > > + u64 baddr; > > + unsigned int max_oa_bits; > > + unsigned int pgshift; > > + unsigned int txsz; > > + int sl; > > + bool hpd; > > + bool be; > > + bool nvhe; > > + bool s2; > > +}; > > + > > +struct s1_walk_result { > > + union { > > + struct { > > + u64 desc; > > + u64 pa; > > + s8 level; > > + u8 APTable; > > + bool UXNTable; > > + bool PXNTable; > > + }; > > + struct { > > + u8 fst; > > + bool ptw; > > + bool s2; > > + }; > > + }; > > + bool failed; > > +}; > > + > > +static void fail_s1_walk(struct s1_walk_result *wr, u8 fst, bool ptw, bool s2) > > +{ > > + wr->fst = fst; > > + wr->ptw = ptw; > > + wr->s2 = s2; > > + wr->failed = true; > > +} > > + > > +#define S1_MMU_DISABLED (-127) > > + > > +static int setup_s1_walk(struct kvm_vcpu *vcpu, struct s1_walk_info *wi, > > + struct s1_walk_result *wr, const u64 va, const int el) > > +{ > > + u64 sctlr, tcr, tg, ps, ia_bits, ttbr; > > + unsigned int stride, x; > > + bool va55, tbi; > > + > > + wi->nvhe = el == 2 && !vcpu_el2_e2h_is_set(vcpu); > > Where 'el' is computed in handle_at_slow() as: > > /* > * We only get here from guest EL2, so the translation regime > * AT applies to is solely defined by {E2H,TGE}. > */ > el = (vcpu_el2_e2h_is_set(vcpu) && > vcpu_el2_tge_is_set(vcpu)) ? 2 : 1; > > I think 'nvhe' will always be false ('el' is 2 only when E2H is > set). Yeah, there is a number of problems here. el should depend on both the instruction (some are EL2-specific) and the HCR control bits. I'll tackle that now. > I'm curious about what 'el' represents. The translation regime for the AT > instruction? Exactly that. Thanks, M. -- Without deviation from the norm, progress is not possible.