From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1D6503E5EEE; Tue, 14 Jul 2026 11:45:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784029539; cv=none; b=IYXskNT59TnzfIE0j0anLTdVpkQD3FybR6CFhiDeaZJi+KEVMo2c9qQCmzEtFk+ixX50jI34CXZCVa6DuUA0wRNnIJd7TqG6YWvh9PLs5jTyFQ30AtZWgT8PlIRy2Q34UqlfGAeeyt4AkOvvAvqXOnQwA8kSGjdHicMN8HApI0U= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784029539; c=relaxed/simple; bh=fBVpdh3rsXHwBqtEJ2zKfACA4KEizfxpM5NCBzcP5vY=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=p2NBzBm92V+CSc41snwN3XIWKZJ043QcJ71Omb51HUg5ODAtChne9bq4qvxz+2uoHQusRce0k/YKXl6ezXR6Hmw3aYtAJr3rxincgkJJe90XtmFCRIxT8eL7c+ErS/82eUlani6H/qQOlz6Y5phqtI1CUcf67TWCbT57a7WAfDo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=eYyK/rA5; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="eYyK/rA5" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B2A951F0155A; Tue, 14 Jul 2026 11:45:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1784029536; bh=hdnDRynVsjFZmm5N9mp8p9XBLkvOBQQB67zloRfXPK4=; h=Date:From:To:Cc:Subject:In-Reply-To:References; b=eYyK/rA5bi3WdR7e49YSnotZ2FXEAt5E52KH+SzpvMFWYeKuVRnaM3vya704bhmZv U1nxMFhlmkXO4Xj/jKoxntjd0nzrhgafZy6IutsvWBPs5DvVAzZjbHWtTKgJ/Zqm0b 6hu39ujo0lOtZ9AsXqz9y6owew5Dv7KLATyMTFEr3Ayeys6X4Ug3DYkSN9nSPERAAX wIOHZ5Q80YotnVPaaEQ7pxFH04zdhXL3mx3iDdxtBomeEskqzxBrmyo7O6paNadJS9 +PZlo2Xn68nW1D6i2hvVkUu9qj8FvNQ/UXQ5OKapqTaUaZd6fVx5cpLWIUtsooW1da FwDCQJpQVBSqQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1wjbZu-00000004rk1-43gs; Tue, 14 Jul 2026 11:45:35 +0000 Date: Tue, 14 Jul 2026 12:45:34 +0100 Message-ID: <86wluxokv5.wl-maz@kernel.org> From: Marc Zyngier To: sashiko-reviews@lists.linux.dev Cc: kvm@vger.kernel.org, kvmarm@lists.linux.dev, "Oliver\ Upton" , Fuad Tabba Subject: Re: [PATCH v2 12/28] arm64: Add FEAT_NV2p1 detection In-Reply-To: <20260714094609.4ACD11F00A3E@smtp.kernel.org> References: <20260714091641.1970822-1-maz@kernel.org> <20260714091641.1970822-13-maz@kernel.org> <20260714094609.4ACD11F00A3E@smtp.kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: sashiko-reviews@lists.linux.dev, kvm@vger.kernel.org, kvmarm@lists.linux.dev, oupton@kernel.org, fuad.tabba@linux.dev X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false + Fuad. On Tue, 14 Jul 2026 10:46:08 +0100, sashiko-bot@kernel.org wrote: > > Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: > - [Medium] Missing immediate Context Synchronization Event (isb) after writing to control-plane system registers cnthctl_el2 and cntkctl_el1. > -- > > --- Patch [12]: [PATCH v2 12/28] arm64: Add FEAT_NV2p1 detection --- > commit e272e43dc6ce85d3337902d78430aad6bf5b83fc > Author: Marc Zyngier > > KVM: arm64: Relax CNTHCTL_EL2 handling when FEAT_NV2p1 is present > > This commit relaxes the handling of CNTHCTL_EL2 when FEAT_NV2p1 is present. > It removes the need for a split approach to access bits and instead relies > on the normal CNTKCTL_EL1 accessor. > > > diff --git a/arch/arm64/kvm/arch_timer.c b/arch/arm64/kvm/arch_timer.c > > index 4155fe89b58a1..db60facad9f3c 100644 > > --- a/arch/arm64/kvm/arch_timer.c > > +++ b/arch/arm64/kvm/arch_timer.c > > @@ -876,8 +876,14 @@ static void timer_set_traps(struct kvm_vcpu *vcpu, struct timer_map *map) > > assign_clear_set_bit(tvt02, CNTHCTL_EL1NVVCT, clr, set); > > assign_clear_set_bit(tpt02, CNTHCTL_EL1NVPCT, clr, set); > > > > - /* This only happens on VHE, so use the CNTHCTL_EL2 accessor. */ > > - sysreg_clear_set(cnthctl_el2, clr, set); > > + /* > > + * This only happens on VHE, so use the CNTHCTL_EL2 accessor, unless > > + * we are sure CNTKCTL_EL1 is completely stateful with FEAT_NV2p1. > > + */ > > + if (!cpus_have_final_cap(ARM64_HAS_NV2P1)) > > + sysreg_clear_set(cnthctl_el2, clr, set); > > + else > > + sysreg_clear_set(cntkctl_el1, clr, set); > > [Severity: Medium] > Does this code need an immediate context synchronization event after writing > to these control-plane system registers? No. > > Modifying cntkctl_el1 (and cnthctl_el2) via sysreg_clear_set() expands to a > conditional write_sysreg() without an immediate isb() barrier. The function > returns immediately after, which may allow intervening instructions to execute > with architecturally undefined pipeline state before a context synchronization > event occurs. > > This path is reachable during normal VM execution when loading vCPU timer > state. While the cnthctl_el2 write is pre-existing, the cntkctl_el1 write > was newly introduced here, which could introduce a regression. No. Fuad, can we please either teach Sashiko about out of context register updates not immediate requiring synchronisation? The constant insistence on having ISBs all over the map is pushing people in doing the wrong thing. Thanks, M. -- Without deviation from the norm, progress is not possible.