From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 45743BA34; Tue, 11 Mar 2025 09:47:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741686435; cv=none; b=EqURWO12Y7Z+p8SQPySuBsfLIOo1m0qS9wqVme0Z0HlqwsOvJsR2u1JbXXFiVKmzE6N8LynVWl6w5wJO68NpB4kLVDE/oJ1JCCK35wIrLpmHY0rWdQQ5JY0W2gu2pNaNrSMv44czxlxVs8xVc666eaHUheFReXyWD6KWRo3dak0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741686435; c=relaxed/simple; bh=m8GtSASoTKItJBBxR++EYkWDcnQaVyq2qcdQfxdQw0Q=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=gZhAM7M/dz+Q2EbJqRF/ZQ/dL4XcnHU5uN8s/Nt6U443fT084HwJ7zgLYx5e4ZQAzjCPlftF5D+3Byps1/ZAPyUTNeIhfKtReLWr6iJE6ORqtvbmDVroG/otNQfcb/5vNy+Ai/BJA3SMXCtsRZtpsgPvCswXidSQGBfPpCyBzwI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=YqpnwX9B; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="YqpnwX9B" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B3D57C4CEE9; Tue, 11 Mar 2025 09:47:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1741686434; bh=m8GtSASoTKItJBBxR++EYkWDcnQaVyq2qcdQfxdQw0Q=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=YqpnwX9B2JRyJ6ffnkz3XHwibH3H3cz+fKM7rFClRH42y0w7kEVeC6u6lz8wUqISl vTC1Q9lEiea8HUF3BMsUXFRnMB6g//gY9uy6QvxySDgdN239b7u2sA/EnQ3ICQLCW5 S+vyETyiQh89sUgQ1LcKHa0g0J5vnY7YthLDoTTTRnyvKt0ZF4SNX3C9b+TxDj8UMA HWFye28XUeXvz8s/V6KAQm+wzS+ZbzcdDZaPMcpSHNU98jePa1d55AvLIzMrDyo69a j31njN3HxtBFCUtx2LUliEwEp0MokEQo7zSkZAyXeJQTPaMhfuoxoUfIT8AGWg5JCh f272CICu68NHQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1trwCe-00CTdL-GR; Tue, 11 Mar 2025 09:47:12 +0000 Date: Tue, 11 Mar 2025 09:47:12 +0000 Message-ID: <86wmcvoq5b.wl-maz@kernel.org> From: Marc Zyngier To: Zhenyu Ye Cc: , , , , , , , , , , , Subject: Re: [PATCH v1 2/5] arm64/kvm: support set the DBM attr during memory abort In-Reply-To: <20250311040321.1460-3-yezhenyu2@huawei.com> References: <20250311040321.1460-1-yezhenyu2@huawei.com> <20250311040321.1460-3-yezhenyu2@huawei.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.4 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: yezhenyu2@huawei.com, yuzenghui@huawei.com, will@kernel.org, oliver.upton@linux.dev, catalin.marinas@arm.com, joey.gouly@arm.com, linux-kernel@vger.kernel.org, xiexiangyou@huawei.com, zhengchuan@huawei.com, wangzhou1@hisilicon.com, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, kvmarm@lists.linux.dev X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Please follow the current convention for the subject of your patch (if you do a git log --oneline on arch/arm64/kvm, all commit should have the same style). On Tue, 11 Mar 2025 04:03:18 +0000, Zhenyu Ye wrote: > > From: eillon > > Since the ARMv8, the page entry has supported the DBM attribute. > Support set the attr during user_mem_abort(). Not quite. ARMv8.1 added DBM, and that is still, to this day, an optional functionality, including in ARMv9.5. > > Signed-off-by: eillon > --- > arch/arm64/include/asm/kvm_pgtable.h | 3 +++ > arch/arm64/kvm/hyp/pgtable.c | 6 ++++++ > 2 files changed, 9 insertions(+) > > diff --git a/arch/arm64/include/asm/kvm_pgtable.h b/arch/arm64/include/asm/kvm_pgtable.h > index 6b9d274052c7..35648d7f08f5 100644 > --- a/arch/arm64/include/asm/kvm_pgtable.h > +++ b/arch/arm64/include/asm/kvm_pgtable.h > @@ -86,6 +86,8 @@ typedef u64 kvm_pte_t; > > #define KVM_PTE_LEAF_ATTR_HI_S2_XN BIT(54) > > +#define KVM_PTE_LEAF_ATTR_HI_S2_DBM BIT(51) > + > #define KVM_PTE_LEAF_ATTR_HI_S1_GP BIT(50) > > #define KVM_PTE_LEAF_ATTR_S2_PERMS (KVM_PTE_LEAF_ATTR_LO_S2_S2AP_R | \ > @@ -252,6 +254,7 @@ enum kvm_pgtable_prot { > > KVM_PGTABLE_PROT_DEVICE = BIT(3), > KVM_PGTABLE_PROT_NORMAL_NC = BIT(4), > + KVM_PGTABLE_PROT_DBM = BIT(5), > > KVM_PGTABLE_PROT_SW0 = BIT(55), > KVM_PGTABLE_PROT_SW1 = BIT(56), > diff --git a/arch/arm64/kvm/hyp/pgtable.c b/arch/arm64/kvm/hyp/pgtable.c > index df5cc74a7dd0..3ea6bdbc02a0 100644 > --- a/arch/arm64/kvm/hyp/pgtable.c > +++ b/arch/arm64/kvm/hyp/pgtable.c > @@ -700,6 +700,9 @@ static int stage2_set_prot_attr(struct kvm_pgtable *pgt, enum kvm_pgtable_prot p > if (prot & KVM_PGTABLE_PROT_W) > attr |= KVM_PTE_LEAF_ATTR_LO_S2_S2AP_W; > > + if (prot & KVM_PGTABLE_PROT_DBM) > + attr |= KVM_PTE_LEAF_ATTR_HI_S2_DBM; > + > if (!kvm_lpa2_is_enabled()) > attr |= FIELD_PREP(KVM_PTE_LEAF_ATTR_LO_S2_SH, sh); > > @@ -1309,6 +1312,9 @@ int kvm_pgtable_stage2_relax_perms(struct kvm_pgtable *pgt, u64 addr, > if (prot & KVM_PGTABLE_PROT_W) > set |= KVM_PTE_LEAF_ATTR_LO_S2_S2AP_W; > > + if (prot & KVM_PGTABLE_PROT_DBM) > + set |= KVM_PTE_LEAF_ATTR_HI_S2_DBM; > + Why isn't that exclusive of PROT_W? > if (prot & KVM_PGTABLE_PROT_X) > clr |= KVM_PTE_LEAF_ATTR_HI_S2_XN; > What is driving this KVM_PGTABLE_PROT_DBM bit? Thanks, M. -- Without deviation from the norm, progress is not possible.