From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 16BD2C7619A for ; Mon, 27 Mar 2023 10:40:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233616AbjC0Kkh (ORCPT ); Mon, 27 Mar 2023 06:40:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54936 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230251AbjC0Kkf (ORCPT ); Mon, 27 Mar 2023 06:40:35 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1DDE140D7 for ; Mon, 27 Mar 2023 03:40:33 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 24896B80C71 for ; Mon, 27 Mar 2023 10:40:32 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B3836C433EF; Mon, 27 Mar 2023 10:40:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1679913630; bh=MLUEj2k+ceEimX+WFyAf1QEdRbUwPo4eXDX3agS/ICU=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=EDF5Ko60haPEZQuHiG2BX5k0B3BPWedla+clTLBmd9VF1MWcNw0HuxohARnZU0IFv qbfwg6fRiMST7n2ZZ07sf10n2spOA9tsE321sGKxXCaA6KNn2sHsB4tigGa3N5lz4y wcBXF4+MYilFQg0QuJ4E9VsJLylLHY7f4fs3wwnFE9PUAugwZLTrsz4CQlA6cQLupH HyKQw/U5WDlO2seoIghZxHewiQi4VVw24a+nJtC4om2JUzn3sdEuqb5LirCfw57wjM oHotJbmz/Ab4tyi1xCVPdRRJ9b8z/zjeGxvfoYED3BCVzCNO9MWQ0t4BTPLWQ7RQWf d+e3aDjHn1lZQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1pgkH6-003Q2U-LF; Mon, 27 Mar 2023 11:40:28 +0100 Date: Mon, 27 Mar 2023 11:40:28 +0100 Message-ID: <86y1niwk83.wl-maz@kernel.org> From: Marc Zyngier To: Jing Zhang Cc: KVM , KVMARM , ARMLinux , Oliver Upton , Will Deacon , Paolo Bonzini , James Morse , Alexandru Elisei , Suzuki K Poulose , Fuad Tabba , Reiji Watanabe , Ricardo Koller , Raghavendra Rao Ananta Subject: Re: [PATCH v4 4/6] KVM: arm64: Use per guest ID register for ID_AA64DFR0_EL1.PMUVer In-Reply-To: <20230317050637.766317-5-jingzhangos@google.com> References: <20230317050637.766317-1-jingzhangos@google.com> <20230317050637.766317-5-jingzhangos@google.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: jingzhangos@google.com, kvm@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, oupton@google.com, will@kernel.org, pbonzini@redhat.com, james.morse@arm.com, alexandru.elisei@arm.com, suzuki.poulose@arm.com, tabba@google.com, reijiw@google.com, ricarkol@google.com, rananta@google.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On Fri, 17 Mar 2023 05:06:35 +0000, Jing Zhang wrote: > > With per guest ID registers, PMUver settings from userspace > can be stored in its corresponding ID register. > > No functional change intended. > > Signed-off-by: Jing Zhang > --- > arch/arm64/include/asm/kvm_host.h | 11 +++--- > arch/arm64/kvm/arm.c | 6 --- > arch/arm64/kvm/id_regs.c | 61 +++++++++++++++++++++++++------ > include/kvm/arm_pmu.h | 5 ++- > 4 files changed, 59 insertions(+), 24 deletions(-) > > diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h > index e926ea91a73c..102860ba896d 100644 > --- a/arch/arm64/include/asm/kvm_host.h > +++ b/arch/arm64/include/asm/kvm_host.h > @@ -218,6 +218,12 @@ struct kvm_arch { > #define KVM_ARCH_FLAG_EL1_32BIT 4 > /* PSCI SYSTEM_SUSPEND enabled for the guest */ > #define KVM_ARCH_FLAG_SYSTEM_SUSPEND_ENABLED 5 > + /* > + * AA64DFR0_EL1.PMUver was set as ID_AA64DFR0_EL1_PMUVer_IMP_DEF > + * or DFR0_EL1.PerfMon was set as ID_DFR0_EL1_PerfMon_IMPDEF from > + * userspace for VCPUs without PMU. > + */ > +#define KVM_ARCH_FLAG_VCPU_HAS_IMP_DEF_PMU 6 > > unsigned long flags; > > @@ -230,11 +236,6 @@ struct kvm_arch { > > cpumask_var_t supported_cpus; > > - struct { > - u8 imp:4; > - u8 unimp:4; > - } dfr0_pmuver; > - > /* Hypercall features firmware registers' descriptor */ > struct kvm_smccc_features smccc_feat; > > diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c > index c78d68d011cb..fb2de2cb98cb 100644 > --- a/arch/arm64/kvm/arm.c > +++ b/arch/arm64/kvm/arm.c > @@ -138,12 +138,6 @@ int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) > kvm_arm_set_default_id_regs(kvm); > kvm_arm_init_hypercalls(kvm); > > - /* > - * Initialise the default PMUver before there is a chance to > - * create an actual PMU. > - */ > - kvm->arch.dfr0_pmuver.imp = kvm_arm_pmu_get_pmuver_limit(); > - > return 0; > > err_free_cpumask: > diff --git a/arch/arm64/kvm/id_regs.c b/arch/arm64/kvm/id_regs.c > index b60ca1058301..3a87a3d2390d 100644 > --- a/arch/arm64/kvm/id_regs.c > +++ b/arch/arm64/kvm/id_regs.c > @@ -21,9 +21,12 @@ > static u8 vcpu_pmuver(const struct kvm_vcpu *vcpu) > { > if (kvm_vcpu_has_pmu(vcpu)) > - return vcpu->kvm->arch.dfr0_pmuver.imp; > - > - return vcpu->kvm->arch.dfr0_pmuver.unimp; > + return FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer), > + vcpu->kvm->arch.id_regs[IDREG_IDX(SYS_ID_AA64DFR0_EL1)]); > + else if (test_bit(KVM_ARCH_FLAG_VCPU_HAS_IMP_DEF_PMU, &vcpu->kvm->arch.flags)) > + return ID_AA64DFR0_EL1_PMUVer_IMP_DEF; > + else > + return 0; Drop the pointless elses. > } > > static u8 perfmon_to_pmuver(u8 perfmon) > @@ -256,10 +259,23 @@ static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, > if (val) > return -EINVAL; > > - if (valid_pmu) > - vcpu->kvm->arch.dfr0_pmuver.imp = pmuver; > - else > - vcpu->kvm->arch.dfr0_pmuver.unimp = pmuver; > + if (valid_pmu) { > + mutex_lock(&vcpu->kvm->lock); Bingo! > + vcpu->kvm->arch.id_regs[IDREG_IDX(SYS_ID_AA64DFR0_EL1)] &= > + ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer); > + vcpu->kvm->arch.id_regs[IDREG_IDX(SYS_ID_AA64DFR0_EL1)] |= > + FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer), pmuver); > + > + vcpu->kvm->arch.id_regs[IDREG_IDX(SYS_ID_DFR0_EL1)] &= > + ~ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon); > + vcpu->kvm->arch.id_regs[IDREG_IDX(SYS_ID_DFR0_EL1)] |= FIELD_PREP( > + ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon), pmuver_to_perfmon(pmuver)); > + mutex_unlock(&vcpu->kvm->lock); > + } else if (pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF) { > + set_bit(KVM_ARCH_FLAG_VCPU_HAS_IMP_DEF_PMU, &vcpu->kvm->arch.flags); > + } else { > + clear_bit(KVM_ARCH_FLAG_VCPU_HAS_IMP_DEF_PMU, &vcpu->kvm->arch.flags); > + } The last two cases are better written as: assign_bit(KVM_ARCH_FLAG_VCPU_HAS_IMP_DEF_PMU, &vcpu->kvm->arch.flags, pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF); > > return 0; > } > @@ -296,10 +312,23 @@ static int set_id_dfr0_el1(struct kvm_vcpu *vcpu, > if (val) > return -EINVAL; > > - if (valid_pmu) > - vcpu->kvm->arch.dfr0_pmuver.imp = perfmon_to_pmuver(perfmon); > - else > - vcpu->kvm->arch.dfr0_pmuver.unimp = perfmon_to_pmuver(perfmon); > + if (valid_pmu) { > + mutex_lock(&vcpu->kvm->lock); Same here (lock inversion) > + vcpu->kvm->arch.id_regs[IDREG_IDX(SYS_ID_DFR0_EL1)] &= > + ~ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon); > + vcpu->kvm->arch.id_regs[IDREG_IDX(SYS_ID_DFR0_EL1)] |= FIELD_PREP( > + ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon), perfmon); > + > + vcpu->kvm->arch.id_regs[IDREG_IDX(SYS_ID_AA64DFR0_EL1)] &= > + ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer); > + vcpu->kvm->arch.id_regs[IDREG_IDX(SYS_ID_AA64DFR0_EL1)] |= FIELD_PREP( > + ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer), perfmon_to_pmuver(perfmon)); > + mutex_unlock(&vcpu->kvm->lock); > + } else if (perfmon == ID_DFR0_EL1_PerfMon_IMPDEF) { > + set_bit(KVM_ARCH_FLAG_VCPU_HAS_IMP_DEF_PMU, &vcpu->kvm->arch.flags); > + } else { > + clear_bit(KVM_ARCH_FLAG_VCPU_HAS_IMP_DEF_PMU, &vcpu->kvm->arch.flags); > + } Same here (assign_bit). > > return 0; > } > @@ -543,4 +572,14 @@ void kvm_arm_set_default_id_regs(struct kvm *kvm) > } > > kvm->arch.id_regs[IDREG_IDX(SYS_ID_AA64PFR0_EL1)] = val; > + > + /* > + * Initialise the default PMUver before there is a chance to > + * create an actual PMU. > + */ > + kvm->arch.id_regs[IDREG_IDX(SYS_ID_AA64DFR0_EL1)] &= > + ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer); > + kvm->arch.id_regs[IDREG_IDX(SYS_ID_AA64DFR0_EL1)] |= > + FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer), > + kvm_arm_pmu_get_pmuver_limit()); Please put these assignments on a single line... > } > diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h > index 628775334d5e..51c7f3e7bdde 100644 > --- a/include/kvm/arm_pmu.h > +++ b/include/kvm/arm_pmu.h > @@ -92,8 +92,9 @@ void kvm_vcpu_pmu_restore_host(struct kvm_vcpu *vcpu); > /* > * Evaluates as true when emulating PMUv3p5, and false otherwise. > */ > -#define kvm_pmu_is_3p5(vcpu) \ > - (vcpu->kvm->arch.dfr0_pmuver.imp >= ID_AA64DFR0_EL1_PMUVer_V3P5) > +#define kvm_pmu_is_3p5(vcpu) \ > + (FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer), \ > + vcpu->kvm->arch.id_regs[IDREG_IDX(SYS_ID_AA64DFR0_EL1)]) >= ID_AA64DFR0_EL1_PMUVer_V3P5) I'll stop mentioning the need for accessors... Thanks, M. -- Without deviation from the norm, progress is not possible.