From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7D9FA1EE7D9; Sat, 21 Dec 2024 09:57:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734775068; cv=none; b=W/OyvzrGGltXiIj6a9+zS2YduhC9EOzLSreolXyGuTZ2IdALOG3m74bmmEsWsMyUiIOu8wRPYXBTP+5FwrAjw+NYuJqteGGhH58XcKgl9HfkoVosWkZ+23CYayElLNv0gLJZTyKSyHxxTqdljXy0HKzsfu/KKxzlFRFE+dAA6VQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734775068; c=relaxed/simple; bh=cA6hokD0aqM2pcntllYiH12JP8LjCCMtE3OBF6ZIU2E=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=MUlj6t6Tb82WQjIbpDsmqQU5PjrgSGEaikqkmj9OYTBoLgTGfSrpzyP2XFutLeX+f4WJciY//e+W8rfI4j7hkh8PdvrjXKXxBr/rN8GAhr0CLkNFz2GLFijQ5JurB29v2Lf+MP/Uw5CmQhK6rGaiOn9rmS4tuI9xpHX4paEiWPg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=DXIavt0c; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="DXIavt0c" Received: by smtp.kernel.org (Postfix) with ESMTPSA id CB42DC4CECE; Sat, 21 Dec 2024 09:57:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1734775067; bh=cA6hokD0aqM2pcntllYiH12JP8LjCCMtE3OBF6ZIU2E=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=DXIavt0ctCzoRX6EWaFKlPy82zEACQJDe+Dy1mSS0OhpFN+1N4KNG+FFMTl1+ADv3 OhxofaFzqqou8Osw/eOxOX/YcfWtMpQe/+LoVXJLj1nRvvB2BYf/m0YzPXFMKytp1Y P1OmYOcAMAuxK/W0ypddKUw2tgSuv923hTIx0HYOb+BZJIMUHmaYgXlaspkPCG4RjW NqNKzvVNGRRdRRqIY1o6Yt7dG9upzA+w8nVJ4qiKTA4S2Pa/TDfgkl97xE1T7lfwp2 POWK/P3oLwsWUn+iC5uA36EXyJ7oEIbSnMM2QJus3XD5+WWvhfKx7qvTHl4bQ8VrlV YyJLgGqsldSkQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1tOwEz-005u3E-7c; Sat, 21 Dec 2024 09:57:45 +0000 Date: Sat, 21 Dec 2024 09:57:44 +0000 Message-ID: <874j2xs6hz.wl-maz@kernel.org> From: Marc Zyngier To: Oliver Upton Cc: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, Joey Gouly , Suzuki K Poulose , Zenghui Yu , Bjorn Andersson , Christoffer Dall , Ganapatrao Kulkarni , Chase Conklin , Eric Auger Subject: Re: [PATCH v2 01/12] KVM: arm64: nv: Add handling of EL2-specific timer registers In-Reply-To: References: <20241217142321.763801-1-maz@kernel.org> <20241217142321.763801-2-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.4 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: oliver.upton@linux.dev, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, andersson@kernel.org, christoffer.dall@arm.com, gankulkarni@os.amperecomputing.com, chase.conklin@arm.com, eauger@redhat.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Sat, 21 Dec 2024 01:38:28 +0000, Oliver Upton wrote: > > On Tue, Dec 17, 2024 at 02:23:09PM +0000, Marc Zyngier wrote: > > @@ -3879,9 +4020,11 @@ static const struct sys_reg_desc cp15_64_regs[] = { > > { SYS_DESC(SYS_AARCH32_CNTPCT), access_arch_timer }, > > { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR1_EL1 }, > > { Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */ > > + { SYS_DESC(SYS_AARCH32_CNTVCT), access_arch_timer }, > > { Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */ > > { SYS_DESC(SYS_AARCH32_CNTP_CVAL), access_arch_timer }, > > { SYS_DESC(SYS_AARCH32_CNTPCTSS), access_arch_timer }, > > + { SYS_DESC(SYS_AARCH32_CNTVCTSS), access_arch_timer }, > > }; > > Huh. You know, I had always thought we hid 32-bit EL0 from nested > guests, but I now realize that isn't the case. Of course, we don't have > the necessary trap reflection for exits that came out of a 32-bit EL0, > nor should we bother. > > Of the 4 NV2 implementations I'm aware of (Neoverse-V1, Neoverse-V2, > AmpereOne, M2) only Neoverse-V1 supports 32-bit userspace. And even > then, a lot of deployments of V1 have a broken NV2 implementation. > > What do you think about advertising a 64-bit only EL0 for nested VMs? I'm completely OK with that. Actually, we already nuke the guest if exiting from 32bit context, no matter the EL (vcpu_mode_is_bad_32bit() is where this happens). But we're missing the ID_AA64PFR0_EL1.EL0 sanitising, which is a bug. I'll send a patch shortly. Now, for this particular patch, I still think we should gracefully handle access to the EL1 timer from a 32bit capable, non-NV guest. Just in case we end-up with a CPU with a broken CNTVOFF_EL2 *and* 32bit capability. In the end, it doesn't cost us much to support this case, and it helps that we can verify that we handle all registers without exception. Thoughts? M. -- Without deviation from the norm, progress is not possible.