From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4A5E7C10F1B for ; Sat, 24 Dec 2022 12:19:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231135AbiLXMTr (ORCPT ); Sat, 24 Dec 2022 07:19:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42992 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229615AbiLXMTp (ORCPT ); Sat, 24 Dec 2022 07:19:45 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CFD7AD10C; Sat, 24 Dec 2022 04:19:44 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 6A3DB6098A; Sat, 24 Dec 2022 12:19:44 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id BD3F7C433D2; Sat, 24 Dec 2022 12:19:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1671884383; bh=7UnOgNqNNGkq1j7WPH+xcgypxvXyh8WRz4m5mCEWNZk=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=E/G4HzOUKAk4mtpPu05c6/cGgYsSlTFgrDa70JvlD7S3x2fhnr7/HHh51JKs9UK7E ZdAnRCRhZkLzfmJFFK52Gb6NxlIfZ+UXd4tkzFNta0SFWLu3F4jkHgc1PbY/zXmfgE MgpwqBJe5tSZtFF2NQErKLmPMR3FBko+TX2ejupaosYucx3zvwAJb8MNVGp8wzSOBp PbIntcez+NbcasbEut/mIq1PlZWIt/LbFVAlmto2QMo4DvRRyvkEWqtpsFstzo/8UN dTJezRaA9eIH7NxZZKtWqPIB+NzMs5MHVuqJKaUW6FISEAf27qJvIerEovWTvJA5um 7Vz/fccD0jDFw== Received: from host81-132-227-111.range81-132.btcentralplus.com ([81.132.227.111] helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1p93V7-00EuoY-Bv; Sat, 24 Dec 2022 12:19:41 +0000 Date: Sat, 24 Dec 2022 12:18:16 +0000 Message-ID: <877cyhf113.wl-maz@kernel.org> From: Marc Zyngier To: Ard Biesheuvel Cc: kvmarm@lists.cs.columbia.edu, kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Suzuki K Poulose , Alexandru Elisei , Oliver Upton , Will Deacon , Quentin Perret , stable@vger.kernel.org Subject: Re: [PATCH 1/3] KVM: arm64: Fix S1PTW handling on RO memslots In-Reply-To: References: <20221220200923.1532710-1-maz@kernel.org> <20221220200923.1532710-2-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 81.132.227.111 X-SA-Exim-Rcpt-To: ardb@kernel.org, kvmarm@lists.cs.columbia.edu, kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, james.morse@arm.com, suzuki.poulose@arm.com, alexandru.elisei@arm.com, oliver.upton@linux.dev, will@kernel.org, qperret@google.com, stable@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On Thu, 22 Dec 2022 13:01:55 +0000, Ard Biesheuvel wrote: > > On Tue, 20 Dec 2022 at 21:09, Marc Zyngier wrote: > > > > A recent development on the EFI front has resulted in guests having > > their page tables baked in the firmware binary, and mapped into > > the IPA space as part as a read-only memslot. > > > > Not only this is legitimate, but it also results in added security, > > so thumbs up. However, this clashes mildly with our handling of a S1PTW > > as a write to correctly handle AF/DB updates to the S1 PTs, and results > > in the guest taking an abort it won't recover from (the PTs mapping the > > vectors will suffer freom the same problem...). > > > > So clearly our handling is... wrong. > > > > Instead, switch to a two-pronged approach: > > > > - On S1PTW translation fault, handle the fault as a read > > > > - On S1PTW permission fault, handle the fault as a write > > > > This is of no consequence to SW that *writes* to its PTs (the write > > will trigger a non-S1PTW fault), and SW that uses RO PTs will not > > use AF/DB anyway, as that'd be wrong. > > > > Only in the case described in c4ad98e4b72c ("KVM: arm64: Assume write > > fault on S1PTW permission fault on instruction fetch") do we end-up > > with two back-to-back faults (page being evicted and faulted back). > > I don't think this is a case worth optimising for. > > > > Fixes: c4ad98e4b72c ("KVM: arm64: Assume write fault on S1PTW permission fault on instruction fetch") > > Signed-off-by: Marc Zyngier > > Cc: stable@vger.kernel.org > > Reviewed-by: Ard Biesheuvel > > I have tested this patch on my TX2 with one of the EFI builds in > question, and everything works as before (I never observed the issue > itself) If you get the chance, could you try with non-4kB page sizes? Here, I could only reproduce it with 16kB pages. It was firing like clockwork on Cortex-A55 with that. > > Regression-tested-by: Ard Biesheuvel > > For the record, the EFI build in question targets QEMU/mach-virt and > switches to a set of read-only page tables in emulated NOR flash > straight out of reset, so it can create and populate the real page > tables with MMU and caches enabled. EFI does not use virtual memory or > paging so managing access flags or dirty bits in hardware is unlikely > to add any value, and it is not being used at the moment. And given > that this is emulated NOR flash, any ordinary write to it tears down > the r/o memslot altogether, and kicks the NOR flash emulation in QEMU > into programming mode, which is fully based on MMIO emulation and does > not use a memslot at all. IOW, even if we could figure out what store > the PTW was attempting to do, it is always going to be rejected since > the r/o page tables can only be modified by 'programming' the NOR > flash sector. Indeed, and this would be a pretty dodgy setup anyway. Thanks for having had a look, M. -- Without deviation from the norm, progress is not possible.