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From: Nam Cao <namcao@linutronix.de>
To: Charlie Jenkins via B4 Relay
	<devnull+thecharlesjenkins.gmail.com@kernel.org>,
	Paul Walmsley <pjw@kernel.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Alexandre Ghiti <alex@ghiti.fr>, Anup Patel <anup@brainfault.org>,
	Atish Patra <atish.patra@linux.dev>,
	Conor Dooley <conor@kernel.org>,
	Paolo Bonzini <pbonzini@redhat.com>,
	Andrew Morton <akpm@linux-foundation.org>,
	Shuah Khan <shuah@kernel.org>
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,
	linux-kselftest@vger.kernel.org,
	Charlie Jenkins <thecharlesjenkins@gmail.com>
Subject: Re: [PATCH 01/16] riscv: Introduce instruction table generation
Date: Wed, 10 Jun 2026 17:56:25 +0200	[thread overview]
Message-ID: <878q8m1j9y.fsf@yellow.woof> (raw)
In-Reply-To: <20260407-riscv_insn_table-v1-1-54b4736a1e77@gmail.com>

Charlie Jenkins via B4 Relay
<devnull+thecharlesjenkins.gmail.com@kernel.org> writes:
> From: Charlie Jenkins <thecharlesjenkins@gmail.com>
>
> Eliminate the need to hand-write riscv instructions by using a shell
> script to autogenerate a header from an instruction table. This is modeled
> after the syscall table infrastructure.
>
> The table is generated externally by riscv-unified-db [1], but is
> in a simple format to make it possible to use other tools or modify
> manually.
>
> [1] https://github.com/riscv-software-src/riscv-unified-db
>
> Signed-off-by: Charlie Jenkins <thecharlesjenkins@gmail.com>

Thanks for the work, I really like the idea. This will make it much
easier to maintain the instruction stuffs.

> +c.ld common,32 011<13|00<0 imm<3=6-5|12-10 xd!1!3!5!7=4-2 xs1=9-7
> +c.ld common,64 011<13|00<0 imm<3=6-5|12-10 xd=4-2 xs1=9-7

Not sure if I confuse something, but the spec says "C.LD is an
RV64C-only instruction". Why do we have 32 here?

> +echo "#define COMMA ," >> $outfile
> +echo "#define SEMICOLON ;" >> $outfile
> +echo "#define SINGLE_ARG(...) __VA_ARGS__" >> $outfile

Aren't these macro unused?

> +echo >> $outfile
> +
> +grep -E "^[a-z\.0-9]+[[:space:]]+" "$infile" | {
> +    while read name base fixed variables; do
> +        echo "/* $name */"
> +
> +        compressed_name=${name##c.*}
	   ^^^^^^^^^^^^^^^
	   this name is misleading

> +        invalid_inst_functions=""
> +        variable_params=""
> +        constraints=""
> +        match=""
> +        mask=""
> +        make=""
> +
> +        # All compressed instructions start with "c."
> +        size=${compressed_name:+32};
> +        size=${size:-16};
> +
> +        # Replace all . with _
> +        formatted_inst_name=$name
> +        while [ ! ${formatted_inst_name##*.*} ]; do
> +            prefix=${formatted_inst_name%.*}
> +            suffix=${formatted_inst_name##*.}
> +            contains_dot=${formatted_inst_name##*.*}
> +            formatted_inst_name=${contains_dot:-${prefix}_${suffix}}
> +        done

Does the simplier
     formatted_inst_name=$(echo $name | tr '.' '_')
work?

> +            echo "static __always_inline ${type}${size} riscv_insn_${formatted_inst_name}_extract_${variable_name}(u${size} ${insn})"
> +            echo "{"
> +            echo "\treturn ${extract};"
> +            echo "}"
> +            echo "static __always_inline void riscv_insn_${formatted_inst_name}_insert_${variable_name}(u${size} *${insn}, ${type}32 ${var})"
> +            echo "{"
> +            echo "\t*_insn &= ${insert_mask# & };"

Why is this required? Isn't this part always zero at this point?

> +            echo "\t*_insn |= ${insert# | };"
> +            echo "}"
> +
> +            if [ "${only_base}" ]; then
> +                invalid_inst_functions="${invalid_inst_functions}static __always_inline ${type}${size} riscv_insn_${formatted_inst_name}_extract_${variable_name}(u${size} ${insn}) {\n\tpanic(\"${name} is not supported on non ${only_base}-bit systems.\");\n}\n"

Instead of panic(), can we do BUILD_BUG() instead?

Nam

  reply	other threads:[~2026-06-10 15:56 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-04-08  4:45 [PATCH 00/16] riscv: Generate riscv instruction functions Charlie Jenkins via B4 Relay
2026-04-08  4:45 ` [PATCH 01/16] riscv: Introduce instruction table generation Charlie Jenkins via B4 Relay
2026-06-10 15:56   ` Nam Cao [this message]
2026-06-11  1:06     ` Charlie Jenkins
2026-06-11  5:21       ` Nam Cao
2026-04-08  4:45 ` [PATCH 02/16] riscv: alternatives: Use generated instruction headers for patching code Charlie Jenkins via B4 Relay
2026-04-08  4:45 ` [PATCH 03/16] riscv: kgdb: Use generated instruction headers Charlie Jenkins via B4 Relay
2026-06-11  6:08   ` Nam Cao
2026-04-08  4:45 ` [PATCH 04/16] riscv: kprobes: " Charlie Jenkins via B4 Relay
2026-06-11  6:14   ` Nam Cao
2026-06-11  6:22   ` Nam Cao
2026-04-08  4:45 ` [PATCH 05/16] riscv: cfi: " Charlie Jenkins via B4 Relay
2026-04-08  4:45 ` [PATCH 06/16] riscv: Use generated instruction headers for misaligned loads/stores Charlie Jenkins via B4 Relay
2026-04-08  4:45 ` [PATCH 07/16] riscv: kvm: Use generated instruction headers for csr code Charlie Jenkins via B4 Relay
2026-04-08  4:45 ` [PATCH 08/16] riscv: kvm: Fix MMIO emulation for sign-extended insns Charlie Jenkins via B4 Relay
2026-04-08  4:45 ` [PATCH 09/16] KVM: device: Add test device Charlie Jenkins via B4 Relay
2026-04-08  4:45 ` [PATCH 10/16] KVM: riscv: selftests: Add mmio test Charlie Jenkins via B4 Relay
2026-04-08  4:45 ` [PATCH 11/16] riscv: kvm: Use generated instruction headers for mmio emulation Charlie Jenkins via B4 Relay
2026-04-08  4:46 ` [PATCH 12/16] riscv: kvm: Add emulated test csr Charlie Jenkins via B4 Relay
2026-04-08  4:46 ` [PATCH 13/16] KVM: riscv: selftests: Add csr emulation test Charlie Jenkins via B4 Relay
2026-04-08  4:46 ` [PATCH 14/16] riscv: kvm: Use generated instruction headers for csr emulation Charlie Jenkins via B4 Relay
2026-04-08  4:46 ` [PATCH 15/16] riscv: kexec: Use generated instruction headers for kexec relocations Charlie Jenkins via B4 Relay
2026-04-08  4:46 ` [PATCH 16/16] riscv: Remove unused instruction headers Charlie Jenkins via B4 Relay
2026-04-08 17:58 ` [PATCH 1/16] riscv: Introduce instruction table generation Charlie Jenkins

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