From mboxrd@z Thu Jan 1 00:00:00 1970 From: Markus Armbruster Subject: Re: KVM call minutes 2013-01-29 - Port I/O Date: Wed, 30 Jan 2013 14:09:20 +0100 Message-ID: <878v7a24xr.fsf@blackfin.pond.sub.org> References: <871ud4gfoa.fsf@elfo.elfo> <5109065B.4060803@suse.de> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Cc: KVM devel mailing list , Juan Quintela , "Michael S. Tsirkin" , qemu-devel , Alexander Graf , Alon Levy , =?utf-8?Q?Herv=C3=A9?= Poussineau , Gerd Hoffmann , Anthony Liguori , qemu-ppc , Andreas =?utf-8?Q?F=C3=A4rber?= , David Gibson To: Peter Maydell Return-path: In-Reply-To: (Peter Maydell's message of "Wed, 30 Jan 2013 11:48:14 +0000") List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+gceq-qemu-devel=gmane.org@nongnu.org Sender: qemu-devel-bounces+gceq-qemu-devel=gmane.org@nongnu.org List-Id: kvm.vger.kernel.org Peter Maydell writes: > On 30 January 2013 11:39, Andreas F=C3=A4rber wrote: >> Proposal by hpoussin was to move _list_add() code to ISADevice: >> http://lists.gnu.org/archive/html/qemu-devel/2013-01/msg00508.html >> >> Concerns: >> * PCI devices (VGA, QXL) register I/O ports as well >> =3D> above patches add dependency on ISABus to machines >> -> " no mac ever had one" >> =3D> PCIDevice shouldn't use ISA API with NULL ISADevice >> * Lack of avi: Who decides about memory API these days? >> >> armbru and agraf concluded that moving this into ISA is wrong. >> >> =3D> I will drop the remaining ioport patches from above series. >> >> Suggestions on how to proceed with tackling the issue are welcome. > > How does this stuff work on real hardware? I would have > expected that a PCI device registering the fact it has > IO ports would have to do so via the PCI controller it > is plugged into... > > My naive don't-know-much-about-portio suggestion is that this > should work the same way as memory regions: each device > provides portio regions, and the controller for the bus > (ISA or PCI) exposes those to the next layer up, and > something at board level maps it all into the right places. Makes sense me, but I'm naive, too :) For me, "I/O ports" are just an alternate address space some devices have. For instance, x86 CPUs have an extra pin for selecting I/O vs. memory address space. The ISA bus has separate read/write pins for memory and I/O. This isn't terribly special. Mapping address spaces around is what devices bridging buses do. I'd expect a system bus for an x86 CPU to have both a memory and an I/O address space. I'd expect an ISA PC's sysbus - ISA bridge to map both directly. I'd expect an ISA bridge for a sysbus without a separate I/O address space to map the ISA I/O address space into the sysbus's normal address space somehow. PCI ISA bridges have their own rules, but I've gotten away with ignoring the details so far :)