From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EE44516FF54; Mon, 25 Mar 2024 09:23:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711358602; cv=none; b=O3MzRhl94c2nv7q/+modcinanhtA674fKiASn6bN11+KxOBdG1a8rp8g58HpCYvMJ9UpyqF5+fRlC8r6GLRXPICQYawfhLFP0aOIaNy+K1SkSLS0kSVX+U94YUNGgRcK54bLJAIJeeXEMlyFnTVK6/Nxz/c7gursyt9WahCfU18= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711358602; c=relaxed/simple; bh=YKZkvwzVw9ZFcV8yz3/FnQ2KN+/hxmUMLVGJNwzWxqA=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=qmY67U+myZfmc3pXv36vwLg5nuhFdiUTDqF5fihouqFyxBF2LEvBbcjciYoexkq5oAi1LDV1clsa8qEzifmjmgEaHmuX+7tONNigxWWb2N3VnTkhWpjcpqcnOYMMyKi1ELyDNnYHN2HKNykvhCnd0YiAiMhzZOOKr/uccAqp/zw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=oDBsn7AR; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="oDBsn7AR" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7D23CC433F1; Mon, 25 Mar 2024 09:23:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711358601; bh=YKZkvwzVw9ZFcV8yz3/FnQ2KN+/hxmUMLVGJNwzWxqA=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=oDBsn7AR8m1T97lQdOpPdMbxcKa6WJZcog+w3JfUSp5ipYM2eOVY9Bj9p3aCCSHvI OKWrWmylsUv76Nnf/UEDUZ3K7ObK3cjxAlbvuRLFuEmMZH7nvWeMC4ufsMexVe2SaN tWCBr6I2KXL/Ky8osQCp48VvFw1P1kXQnn0JCetYaEbs/pOTswY4Gls/wOZyTE//sT MBR3ax22eHUKA0k1t5eTwCC39Zvt8I1xYGd0PmjqtGy0jhkkq+4koNN0cTGZQ0fQGJ u1qRU8An8b+fbmESSSSFHwl5/5wiYuSxVVGKS80lembgzN8AxYXheGtMkaX/AAxKih NZvHQ0zkWaHnA== Received: from 213-229-0-18.static.upcbusiness.at ([213.229.0.18] helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1rogY3-00FNFl-8R; Mon, 25 Mar 2024 09:23:19 +0000 Date: Mon, 25 Mar 2024 09:23:18 +0000 Message-ID: <87cyrism0p.wl-maz@kernel.org> From: Marc Zyngier To: Mark Brown Cc: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, James Morse , Suzuki K Poulose , Oliver Upton , Zenghui Yu , James Clark , Anshuman Khandual , Dongli Zhang Subject: Re: [PATCH v2 5/5] KVM: arm64: Exclude FP ownership from kvm_vcpu_arch In-Reply-To: <252bc993-e93d-4412-bfc6-13930b80dbd8@sirena.org.uk> References: <20240322170945.3292593-1-maz@kernel.org> <20240322170945.3292593-6-maz@kernel.org> <87edc0sr7z.wl-maz@kernel.org> <252bc993-e93d-4412-bfc6-13930b80dbd8@sirena.org.uk> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 213.229.0.18 X-SA-Exim-Rcpt-To: broonie@kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, james.morse@arm.com, suzuki.poulose@arm.com, oliver.upton@linux.dev, yuzenghui@huawei.com, james.clark@arm.com, anshuman.khandual@arm.com, dongli.zhang@oracle.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Mon, 25 Mar 2024 00:27:43 +0000, Mark Brown wrote: > > > > - Add support for the V registers in the sysreg interface when SVE is > > > enabled. > > > We already support the V registers with KVM_REG_ARM_CORE_REG(). Why > > would you add any new interface for this? The kernel should be > > perfectly capable of dealing with the placement of the data in the > > internal structures, and there is no need to tie the userspace ABI to > > how we deal with that placement (kvm_regs is already purely > > userspace). > > This was referring to the fact that currently when SVE is enabled access > to the V registers as V registers via _CORE_REG() is blocked and they > can only be accessed as a subset of the Z registers (see the check at > the end of core_reg_size_from_offset() in guest.c). But what behaviour do you expect from allowing such a write? Insert in place? Or zero the upper bits of the vector, as per R_WKYLB? One is wrong, and the other wrecks havoc on unsuspecting userspace. My take on this is that when a VM is S*E aware, only the writes to the largest *enabled* registers should take place. This is similar to what we do for FP/SIMD: we only allow writes to the V registers, and not to Q, D, S, H or B, although that happens by construction. For S*E, dropping the write on the floor (or return some error that userspace will understand as benign) is the least bad option. M. -- Without deviation from the norm, progress is not possible.