Re: [Qemu-devel] KVM call minutes 2013-01-29 - Port I/O

[Anthony Liguori <anthony@codemonkey.ws>]

Markus Armbruster <armbru@redhat.com> writes:

> Peter Maydell <peter.maydell@linaro.org> writes:
>
>> On 30 January 2013 11:39, Andreas Färber <afaerber@suse.de> wrote:
>>> Proposal by hpoussin was to move _list_add() code to ISADevice:
>>> http://lists.gnu.org/archive/html/qemu-devel/2013-01/msg00508.html
>>>
>>> Concerns:
>>> * PCI devices (VGA, QXL) register I/O ports as well
>>>   => above patches add dependency on ISABus to machines
>>>      -> "<benh> no mac ever had one"
>>>   => PCIDevice shouldn't use ISA API with NULL ISADevice
>>> * Lack of avi: Who decides about memory API these days?
>>>
>>> armbru and agraf concluded that moving this into ISA is wrong.
>>>
>>> => I will drop the remaining ioport patches from above series.
>>>
>>> Suggestions on how to proceed with tackling the issue are welcome.
>>
>> How does this stuff work on real hardware? I would have
>> expected that a PCI device registering the fact it has
>> IO ports would have to do so via the PCI controller it
>> is plugged into...
>>
>> My naive don't-know-much-about-portio suggestion is that this
>> should work the same way as memory regions: each device
>> provides portio regions, and the controller for the bus
>> (ISA or PCI) exposes those to the next layer up, and
>> something at board level maps it all into the right places.
>
> Makes sense me, but I'm naive, too :)
>
> For me, "I/O ports" are just an alternate address space some devices
> have.  For instance, x86 CPUs have an extra pin for selecting I/O
> vs. memory address space.  The ISA bus has separate read/write pins for
> memory and I/O.
>
> This isn't terribly special.  Mapping address spaces around is what
> devices bridging buses do.
>
> I'd expect a system bus for an x86 CPU to have both a memory and an I/O
> address space.

There is no such thing as a "system bus".

There is a bus that links the CPUs to each other and to the North
Bridge.  This is QPI on modern systems.

Sometimes there's a bus to link the North Bridge to the South Bridge.
On modern systems, this is QPI.  On the i440fx, the i440fx is both the
South Bridge and North Bridge and the link between the two is internal
to the chip.  The South Bridge may then export one or more downstream
interfaces.  In the i440fx, it only exports PCI.

Behind the PCI bus, there may be bridges.  On the i440fx, there is a ISA
Bridge which also acts as a Super I/O chip.  It exposes a downstream ISA
bus.

sysbus is a relic of poor modeling.  A major milestone in QEMU's
evolution will be when sysbus is completely removed.

Regards,

Anthony Liguori

>
> I'd expect an ISA PC's sysbus - ISA bridge to map both directly.
>
> I'd expect an ISA bridge for a sysbus without a separate I/O address
> space to map the ISA I/O address space into the sysbus's normal address
> space somehow.
>
> PCI ISA bridges have their own rules, but I've gotten away with ignoring
> the details so far :)