From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6B938EB64DA for ; Wed, 12 Jul 2023 20:06:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231836AbjGLUGP (ORCPT ); Wed, 12 Jul 2023 16:06:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44804 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229880AbjGLUGN (ORCPT ); Wed, 12 Jul 2023 16:06:13 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9B96F1FE6 for ; Wed, 12 Jul 2023 13:06:12 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 214B6618F8 for ; Wed, 12 Jul 2023 20:06:12 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 84AB0C433C7; Wed, 12 Jul 2023 20:06:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1689192371; bh=cHVf3yeITRqxsgrS58hExLzmnwwO0E8oGYcaFus6958=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=iAxENWyZywKL1WAKLtVXG4U2ZA0kPkAUMLVlQmxoI5hud4lfpY8qMgPPLjnjmAWuX SFkiuQMMmp16w9oOgxUBg4EsEt3ARlyN1HxV1Pw0IVNXsJT2SxrmkC2UgMZnFpXvtB EXHY2LLqYh+3TJTwXrWu+otMX8Ydq0w78lhdUXAB18XG52uy1WKNF+0SStvUKyGK+1 k86/tflefJrULaYJBDWJCp+TRbmwzfBgSgYSPQ85DeKck2GBd24fQyL0hwvtAXc/fa 5V17ighNR2SUV2g248JqcFHB3tY0XUQOtAjeXcfW20JZBvkZsJ9Ti2ZAM1zSS2fux+ FZHYJpy0Fx4+A== Received: from sofa.misterjones.org ([185.219.108.64] helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1qJg6D-00CajL-5B; Wed, 12 Jul 2023 21:06:09 +0100 Date: Wed, 12 Jul 2023 21:06:08 +0100 Message-ID: <87edlcao9b.wl-maz@kernel.org> From: Marc Zyngier To: Mark Brown Cc: kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Catalin Marinas , Eric Auger , Mark Rutland , Will Deacon , Alexandru Elisei , Andre Przywara , Chase Conklin , Ganapatrao Kulkarni , Darren Hart , Miguel Luis , James Morse , Suzuki K Poulose , Oliver Upton , Zenghui Yu Subject: Re: [PATCH 14/27] KVM: arm64: Restructure FGT register switching In-Reply-To: References: <20230712145810.3864793-1-maz@kernel.org> <20230712145810.3864793-15-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: broonie@kernel.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, catalin.marinas@arm.com, eric.auger@redhat.com, mark.rutland@arm.com, will@kernel.org, alexandru.elisei@arm.com, andre.przywara@arm.com, chase.conklin@arm.com, gankulkarni@os.amperecomputing.com, darren@os.amperecomputing.com, miguel.luis@oracle.com, james.morse@arm.com, suzuki.poulose@arm.com, oliver.upton@linux.dev, yuzenghui@huawei.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On Wed, 12 Jul 2023 18:15:41 +0100, Mark Brown wrote: > > On Wed, Jul 12, 2023 at 03:57:57PM +0100, Marc Zyngier wrote: > > > As we're about to majorly extend the handling of FGT registers, > > restructure the code to actually save/restore the registers > > as required. This is made easy thanks to the previous addition > > of the EL2 registers, allowing us to use the host context for > > this purpose. > > > +/* > > + * FGT register definitions > > + * > > + * RES0 and polarity masks as of DDI0487J.a, to be updated as needed. > > + * We're not using the generated masks as they are usually ahead of > > + * the published ARM ARM, which we use as a reference. > > + * > > + * Once we get to a point where the two describe the same thing, we'll > > + * merge the definitions. One day. > > + */ > > What's the issue here? The generated definitions should be aligned with > what's published in DDI0601. That AIUI exists in large part due to > concerns people were having with the amount of time it can take to fold > new features into the ARM, it's official. For multiple reasons: - What's published as DDI0601 is a list of registers, without any context and no relation to the wider architecture (it is basically the XML dumped as a PDF). That's not enough to implement the architecture as it is missing all the content of the engineering specs, which are not public documents. - I have no motivation in supporting the latest and greatest. NV is hard enough without all the (still evolving) crop of 8.9/9.4 extensions. As long as what I have is a legal implementation and runs on the HW I have access to, that's good enough for me. - I want to look at a single document and support what's in there. Not two. Because it is hard enough to follow when you're implementing this crap, and even harder for someone trying to review it. So I firmly intend to totally ignore most of what's outside of the published ARM ARM unless it makes my life so much easier that I can't afford not to implement it. M. -- Without deviation from the norm, progress is not possible.