From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A2AD0C001B0 for ; Tue, 15 Aug 2023 10:40:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236484AbjHOKjy (ORCPT ); Tue, 15 Aug 2023 06:39:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35334 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236390AbjHOKj0 (ORCPT ); Tue, 15 Aug 2023 06:39:26 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 89F4CBB for ; Tue, 15 Aug 2023 03:39:25 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 1345065179 for ; Tue, 15 Aug 2023 10:39:25 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 26BFBC433C7; Tue, 15 Aug 2023 10:39:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1692095964; bh=lGpBpkDsEOQPJi3Zi+iXLacaZpWdyRJMMIhqGUJ9v14=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=g2PHew2j/hTikazRhsHToe3V7GbmJ7igUZipRM0xidxig7apE3lhleU2xsmal5QUG aU46Nl0Dp2+oT0C1Uo20rS6apC5cZo0CdWS0tIxZdnkjyp7hMpk40UIk5XZR1rpRKD Ldln1Nm+VcVs1biv/e50jnI+nu4ND3VrBnhOzaNf5YZpwVT7uDyMyzLAVJKEPAZQCa fGHSLcOZ9XwCZs0/GOnqJtREeLBoL5DR0MWEh5tqMJfAygXhRVh8nQs5Iu97h70iAc Y4lRyDrVwPwV860x1bmLn79IJKtobFh5sh7tc8oxn8B3+kv47H5Itw2cCIuvj7SvKm uzMwNeyJ9HVsg== Received: from host213-123-75-60.in-addr.btopenworld.com ([213.123.75.60] helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1qVrSM-004ydV-37; Tue, 15 Aug 2023 11:39:22 +0100 Date: Tue, 15 Aug 2023 11:39:34 +0100 Message-ID: <87fs4kpp21.wl-maz@kernel.org> From: Marc Zyngier To: Jing Zhang Cc: kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Catalin Marinas , Eric Auger , Mark Brown , Mark Rutland , Will Deacon , Alexandru Elisei , Andre Przywara , Chase Conklin , Ganapatrao Kulkarni , Darren Hart , Miguel Luis , James Morse , Suzuki K Poulose , Oliver Upton , Zenghui Yu Subject: Re: [PATCH v3 19/27] KVM: arm64: nv: Add fine grained trap forwarding infrastructure In-Reply-To: References: <20230808114711.2013842-1-maz@kernel.org> <20230808114711.2013842-20-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 213.123.75.60 X-SA-Exim-Rcpt-To: jingzhangos@google.com, kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, catalin.marinas@arm.com, eric.auger@redhat.com, broonie@kernel.org, mark.rutland@arm.com, will@kernel.org, alexandru.elisei@arm.com, andre.przywara@arm.com, chase.conklin@arm.com, gankulkarni@os.amperecomputing.com, darren@os.amperecomputing.com, miguel.luis@oracle.com, james.morse@arm.com, suzuki.poulose@arm.com, oliver.upton@linux.dev, yuzenghui@huawei.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On Mon, 14 Aug 2023 18:18:57 +0100, Jing Zhang wrote: >=20 > Hi Marc, >=20 > On Tue, Aug 8, 2023 at 4:47=E2=80=AFAM Marc Zyngier wrot= e: > > > > Fine Grained Traps are fun. Not. > > > > Implement the fine grained trap forwarding, reusing the Coarse Grained > > Traps infrastructure previously implemented. > > > > Each sysreg/instruction inserted in the xarray gets a FGT group > > (vaguely equivalent to a register number), a bit number in that registe= r, > > and a polarity. > > > > It is then pretty easy to check the FGT state at handling time, just > > like we do for the coarse version (it is just faster). > > > > Reviewed-by: Eric Auger > > Signed-off-by: Marc Zyngier > > --- > > arch/arm64/kvm/emulate-nested.c | 78 ++++++++++++++++++++++++++++++++- > > 1 file changed, 77 insertions(+), 1 deletion(-) > > > > diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-n= ested.c > > index cd0544c3577e..af75c2775638 100644 > > --- a/arch/arm64/kvm/emulate-nested.c > > +++ b/arch/arm64/kvm/emulate-nested.c > > @@ -928,6 +928,27 @@ static const struct encoding_to_trap_config encodi= ng_to_cgt[] __initconst =3D { > > > > static DEFINE_XARRAY(sr_forward_xa); > > > > +enum fgt_group_id { > > + __NO_FGT_GROUP__, > > + > > + /* Must be last */ > > + __NR_FGT_GROUP_IDS__ > > +}; > > + > > +#define SR_FGT(sr, g, b, p) \ > > + { \ > > + .encoding =3D sr, \ > > + .end =3D sr, \ > > + .tc =3D { \ > > + .fgt =3D g ## _GROUP, \ > > + .bit =3D g ## _EL2_ ## b ## _SHIFT, \ > > + .pol =3D p, \ > > + }, \ > > + } > > + > > +static const struct encoding_to_trap_config encoding_to_fgt[] __initco= nst =3D { > > +}; > > + > > static union trap_config get_trap_config(u32 sysreg) > > { > > return (union trap_config) { > > @@ -941,6 +962,7 @@ int __init populate_nv_trap_config(void) > > > > BUILD_BUG_ON(sizeof(union trap_config) !=3D sizeof(void *)); > > BUILD_BUG_ON(__NR_TRAP_GROUP_IDS__ > BIT(TC_CGT_BITS)); > > + BUILD_BUG_ON(__NR_FGT_GROUP_IDS__ > BIT(TC_FGT_BITS)); > > > > for (int i =3D 0; i < ARRAY_SIZE(encoding_to_cgt); i++) { > > const struct encoding_to_trap_config *cgt =3D &encoding= _to_cgt[i]; > > @@ -963,6 +985,34 @@ int __init populate_nv_trap_config(void) > > kvm_info("nv: %ld coarse grained trap handlers\n", > > ARRAY_SIZE(encoding_to_cgt)); > > > > + if (!cpus_have_final_cap(ARM64_HAS_FGT)) > > + goto check_mcb; > > + > > + for (int i =3D 0; i < ARRAY_SIZE(encoding_to_fgt); i++) { > > + const struct encoding_to_trap_config *fgt =3D &encoding= _to_fgt[i]; > > + union trap_config tc; > > + > > + tc =3D get_trap_config(fgt->encoding); > > + > > + if (tc.fgt) { > > + kvm_err("Duplicate FGT for (%d, %d, %d, %d, %d)= \n", > > + sys_reg_Op0(fgt->encoding), > > + sys_reg_Op1(fgt->encoding), > > + sys_reg_CRn(fgt->encoding), > > + sys_reg_CRm(fgt->encoding), > > + sys_reg_Op2(fgt->encoding)); > > + ret =3D -EINVAL; > > + } > > + > > + tc.val |=3D fgt->tc.val; > > + xa_store(&sr_forward_xa, fgt->encoding, > > + xa_mk_value(tc.val), GFP_KERNEL); > > + } > > + > > + kvm_info("nv: %ld fine grained trap handlers\n", > > + ARRAY_SIZE(encoding_to_fgt)); > > + > > +check_mcb: > > for (int id =3D __MULTIPLE_CONTROL_BITS__; > > id < (__COMPLEX_CONDITIONS__ - 1); > > id++) { > > @@ -1031,13 +1081,26 @@ static enum trap_behaviour compute_trap_behavio= ur(struct kvm_vcpu *vcpu, > > return __do_compute_trap_behaviour(vcpu, tc.cgt, b); > > } > > > > +static bool check_fgt_bit(u64 val, const union trap_config tc) > > +{ > > + return ((val >> tc.bit) & 1) =3D=3D tc.pol; > > +} > > + > > +#define sanitised_sys_reg(vcpu, reg) \ > > + ({ \ > > + u64 __val; \ > > + __val =3D __vcpu_sys_reg(vcpu, reg); \ > > + __val &=3D ~__ ## reg ## _RES0; \ > > + (__val); \ > > + }) > > + > > bool __check_nv_sr_forward(struct kvm_vcpu *vcpu) > > { > > union trap_config tc; > > enum trap_behaviour b; > > bool is_read; > > u32 sysreg; > > - u64 esr; > > + u64 esr, val; > > > > if (!vcpu_has_nv(vcpu) || is_hyp_ctxt(vcpu)) > > return false; > > @@ -1060,6 +1123,19 @@ bool __check_nv_sr_forward(struct kvm_vcpu *vcpu) > > if (!tc.val) > > return false; > > > > + switch ((enum fgt_group_id)tc.fgt) { > > + case __NO_FGT_GROUP__: > > + break; > > + > > + case __NR_FGT_GROUP_IDS__: > > + /* Something is really wrong, bail out */ > > + WARN_ONCE(1, "__NR_FGT_GROUP_IDS__"); > > + return false; >=20 > Do we need a default clause here to catch unexpected tc.fgt values? I'd rather not have anything special at handling time, as the compiler is perfectly allowed to use the cast above to restrict the value to the enumeration. We already cover all the possible enum values, which is good enough. However, I've added an extra check at boot time for unexpected values having sneaked into the FGT table. Thanks, M. --=20 Without deviation from the norm, progress is not possible.