From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.0 required=3.0 tests=BAYES_00,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1185AC43460 for ; Thu, 29 Apr 2021 20:01:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E5152613DA for ; Thu, 29 Apr 2021 20:01:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236969AbhD2UBy (ORCPT ); Thu, 29 Apr 2021 16:01:54 -0400 Received: from mail.kernel.org ([198.145.29.99]:55640 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237301AbhD2UAK (ORCPT ); Thu, 29 Apr 2021 16:00:10 -0400 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 72C3D613C1; Thu, 29 Apr 2021 19:59:22 +0000 (UTC) Received: from 78.163-31-62.static.virginmediabusiness.co.uk ([62.31.163.78] helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94) (envelope-from ) id 1lcCoi-00A5Du-4j; Thu, 29 Apr 2021 20:59:20 +0100 Date: Thu, 29 Apr 2021 20:59:14 +0100 Message-ID: <87fsz8vp4d.wl-maz@kernel.org> From: Marc Zyngier To: Ricardo Koller Cc: kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, pbonzini@redhat.com, drjones@redhat.com, alexandru.elisei@arm.com, eric.auger@redhat.com Subject: Re: [PATCH 1/3] KVM: selftests: Add exception handling support for aarch64 In-Reply-To: References: <20210423040351.1132218-1-ricarkol@google.com> <20210423040351.1132218-2-ricarkol@google.com> <87sg3hnzrj.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: ricarkol@google.com, kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, pbonzini@redhat.com, drjones@redhat.com, alexandru.elisei@arm.com, eric.auger@redhat.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org AOn Thu, 29 Apr 2021 18:51:59 +0100, Ricardo Koller wrote: > > On Fri, Apr 23, 2021 at 09:58:24AM +0100, Marc Zyngier wrote: > > Hi Ricardo, > > > > Thanks for starting this. > > > > On Fri, 23 Apr 2021 05:03:49 +0100, > > Ricardo Koller wrote: > > > +.pushsection ".entry.text", "ax" > > > +.balign 0x800 > > > +.global vectors > > > +vectors: > > > +.popsection > > > + > > > +/* > > > + * Build an exception handler for vector and append a jump to it into > > > + * vectors (while making sure that it's 0x80 aligned). > > > + */ > > > +.macro HANDLER, el, label, vector > > > +handler\()\vector: > > > + save_registers \el > > > + mov x0, sp > > > + mov x1, \vector > > > + bl route_exception > > > + restore_registers \el > > > + > > > +.pushsection ".entry.text", "ax" > > > +.balign 0x80 > > > + b handler\()\vector > > > +.popsection > > > +.endm > > > > That's an interesting construct, wildly different from what we are > > using elsewhere in the kernel, but hey, I like change ;-). It'd be > > good to add a comment to spell out that anything that emits into > > .entry.text between the declaration of 'vectors' and the end of this > > file will break everything. > > > > > + > > > +.global ex_handler_code > > > +ex_handler_code: > > > + HANDLER 1, sync, 0 // Synchronous EL1t > > > + HANDLER 1, irq, 1 // IRQ EL1t > > > + HANDLER 1, fiq, 2 // FIQ EL1t > > > + HANDLER 1, error, 3 // Error EL1t > > > > Can any of these actually happen? As far as I can see, the whole > > selftest environment seems to be designed around EL1h. > > > > They can happen. KVM defaults to use EL1h: That's not a KVM decision. That's an architectural requirement. Reset is an exception, exception use the handler mode. > > #define VCPU_RESET_PSTATE_EL1 (PSR_MODE_EL1h | PSR_A_BIT | PSR_I_BIT | \ > > but then a guest can set the SPSel to 0: > > asm volatile("msr spsel, #0"); > > and this happens: > > Unexpected exception guest (vector:0x0, ec:0x25) > > I think it should still be a valid situation: some test might want to > try it. Sure, but that's not what this test (in patch #2) is doing, is it? If, as I believe, this is an unexpected situation, why not handle it separately? I'm not advocating one way or another, but it'd be good to understand the actual scope of the exception handling in this infrastructure. If you plan to allow tests to run in the EL1t environment, where do you decide to switch back to EL1t after taking the exception in EL1h? Are the tests supposed to implement both stack layouts? Overall, I'm worried that nobody is going to use this layout *unless* it becomes mandated. Thanks, M. -- Without deviation from the norm, progress is not possible.