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[95.120.215.139]) by smtp.gmail.com with ESMTPSA id x16sm3664590wrl.32.2019.09.25.01.40.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Sep 2019 01:40:15 -0700 (PDT) References: <20190924124433.96810-1-slp@redhat.com> <20190924124433.96810-8-slp@redhat.com> <23a6e891-c3ba-3991-d627-433eb1fe156d@redhat.com> <87r245rkld.fsf@redhat.com> <317e53b1-d658-4b6b-c782-4b2a0dd091b2@redhat.com> User-agent: mu4e 1.2.0; emacs 26.2 From: Sergio Lopez To: Paolo Bonzini Cc: qemu-devel@nongnu.org, mst@redhat.com, imammedo@redhat.com, marcel.apfelbaum@gmail.com, rth@twiddle.net, ehabkost@redhat.com, philmd@redhat.com, lersek@redhat.com, kraxel@redhat.com, mtosatti@redhat.com, kvm@vger.kernel.org Subject: Re: [PATCH v4 7/8] docs/microvm.txt: document the new microvm machine type In-reply-to: <317e53b1-d658-4b6b-c782-4b2a0dd091b2@redhat.com> Date: Wed, 25 Sep 2019 10:40:13 +0200 Message-ID: <87ftkksr9u.fsf@redhat.com> MIME-Version: 1.0 Content-Type: multipart/signed; boundary="=-=-="; micalg=pgp-sha256; protocol="application/pgp-signature" Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org --=-=-= Content-Type: text/plain Content-Transfer-Encoding: quoted-printable Paolo Bonzini writes: > On 25/09/19 07:49, Sergio Lopez wrote: >>>> +serving as a stepping stone >>>> +for future projects aiming at improving boot times, reducing the >>>> +attack surface and slimming down QEMU's footprint. >>> >>> "Microvm also establishes a baseline for benchmarking QEMU and operating >>> systems, since it is optimized for both boot time and footprint". >>=20 >> Well, I prefer my paragraph, but I'm good with either. > > You're right my version sort of missed the point. What about > s/benchmarking/benchmarking and optimizing/? > >>>> +The microvm machine type supports the following devices: >>>> + >>>> + - ISA bus >>>> + - i8259 PIC >>>> + - LAPIC (implicit if using KVM) >>>> + - IOAPIC (defaults to kernel_irqchip_split =3D true) >>>> + - i8254 PIT >>> >>> Do we need the PIT? And perhaps the PIC even? >>=20 >> We need the PIT for non-KVM accel (if present with KVM and >> kernel_irqchip_split =3D off, it basically becomes a placeholder) > > Why? Perhaps I'm missing something. Is some other device supposed to be acting as a HW timer while running with TCG acceleration? >> and the >> PIC for both the PIT and the ISA serial port. > > Can't the ISA serial port work with the IOAPIC? Hm... I'm not sure. I wanted to give it a try, but then noticed that multiple places in the code (like hw/intc/apic.c:560) do expect to have an ISA PIC present through the isa_pic global variable. I guess we should be able to work around this, but I'm not sure if it's really worth it. What do you think? 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