From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7F7DF31F9A7; Sun, 26 Apr 2026 14:07:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777212459; cv=none; b=nLG07ymWNvGIxWVQVaaQ/xmos+jKYUpmJbpjf0GCa2yK6sc3yarIOXcOf1hoelXOQkvvPBPWp0lzaO0PIOGMcjeiorHhli1miCtx+J4DqXTgWBf0zqirKsLM5UFz9eEBOcsZWkYxeM9rET1Cf41pm8Y7KujPFEsQG4zrXmUylXQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777212459; c=relaxed/simple; bh=lDY502D0UwTlnUwqf8BtPahtm7twsTmu8HFtn+sm0IA=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=dxM+bv0r8cdHflf5DKClX+cUu4qQriM5w1o7GfQ8F2/F6LE1VVzDwfvn8lh/HehdG+6Xw2O4kj11C+e6sO+qzjW0kgDn5662KqtEb+Cl0tLF55FatYzX7ZZfv4Gj79g0tHKGV1JlIebxIXu61UyiXzE8jcsF1L1YRN084VuXRws= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=tH7DMitl; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="tH7DMitl" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1D9C2C2BCAF; Sun, 26 Apr 2026 14:07:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1777212459; bh=lDY502D0UwTlnUwqf8BtPahtm7twsTmu8HFtn+sm0IA=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=tH7DMitlSokecV8h+r6UW83iqIZELeQsvftYXNCwbWJ4C1tGsegwbFrQwE8VRLIol pdOPTL5FUBTWxqfYLt3YWZOTmZ06lkNOZRAKdTSqbouqHoUEMyemuj1pbvXGPVse2u F/EYw15WAetJgngUM32zjvi9O6m9TA+Ww0qQG9A1qaB5LXBYujRuLmbvLwg/s46wmH XO/Oo18VWtjN1/TECD1FWniOIDDXuN5zmlWI7FaX+lsuxs5VirkvkLZ9axgQN2yLSk XR8Yh/ZDZt64YYJ9u0bBs9jhqEegHr5aFTjc2tTVqXuYVyRs/lSlBUGv7BFwWW+LcU Oew3uCGUnOUdQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=lobster-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1wH092-0000000EnUE-3vU3; Sun, 26 Apr 2026 14:07:37 +0000 Date: Sun, 26 Apr 2026 15:07:36 +0100 Message-ID: <87ik9dbys7.wl-maz@kernel.org> From: Marc Zyngier To: Vishnu Pajjuri Cc: Fuad Tabba , Joey Gouly , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Christoffer Dall , Mark Brown , kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, Darren Hart Subject: Re: [PATCH v4 35/49] KVM: arm64: GICv3: nv: Plug L1 LR sync into deactivation primitive In-Reply-To: <861pg213to.wl-maz@kernel.org> References: <20251120172540.2267180-1-maz@kernel.org> <20251120172540.2267180-36-maz@kernel.org> <2e12c5c2-a1b6-47b7-b54c-7281a77bbe0a@os.amperecomputing.com> <878qb9cxzr.wl-maz@kernel.org> <1e050b67-2276-41ad-9265-796ba853dc7c@os.amperecomputing.com> <86a4vo49ni.wl-maz@kernel.org> <86eck71o1v.wl-maz@kernel.org> <861pg213to.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: vishnu@os.amperecomputing.com, tabba@google.com, joey.gouly@arm.com, suzuki.poulose@arm.com, oupton@kernel.org, yuzenghui@huawei.com, christoffer.dall@arm.com, broonie@kernel.org, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, darren@os.amperecomputing.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Sun, 26 Apr 2026 10:14:11 +0100, Marc Zyngier wrote: > > On Wed, 22 Apr 2026 15:57:44 +0100, > Vishnu Pajjuri wrote: > > > > Hi Marc, > > > > On 22-04-2026 12:25, Marc Zyngier wrote: > > > > > > Have you made progress on this? I can't reproduce it at all despite my > > > best effort. I'm perfectly happy to help, but you need to give me > > > *something* to go on. > > > > > > Thanks for your support!! > > > > The issue is triggered as soon as the timer interrupt (IRQ 27) is > > deactivated. Preventing the deactivation of IRQ 27 during nested VGIC > > state transitions prevents the failure from reproducing. > > Which level of deactivation? From L2 to L1? Or L1 to L0? The former > should just be a an update to the irq structure, while the latter is > effectively a write to ICC_DIR_EL1, and *that* is a new behaviour > introduced by this patch. > > I wonder if your implementation is such that ICC_DIR_EL1 is trapped by > ICH_HCR_EL2.TDIR, which is allowed by the architecture, but that none > of the two implementations I have actually enforce (the trap only > applies to ICV_DIR_EL1). Can you try the hack below which disables the > traps much earlier, and let me know if that helps? > > Even if that's the case, this should result in an EL2->EL2 exception, > and that should be caught as an unhandled exception in entry-common.c, > so something else is afoot. Actually, this should never happen. ICH_HCR_EL2.TDIR is constructed like all the other GICv3 trap bits, in the sense that it only traps accesses from EL1, not EL2 (for sanity reasons, I'm not considering the possibility of a trap to EL3...). Still, I'm interested in finding out if that hack helps at all. Thanks, M. -- Jazz isn't dead. It just smells funny.