From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A1C3A8F6C; Wed, 8 May 2024 06:04:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715148283; cv=none; b=J0fVDeGuCMdTPIiUtZUF8gHHpzwYyDDPRz7mpqZZcweO6WeLYk/DZofXuqS8mlqHHvcYKD6xIroUXw3uhK74RK5MInX9lfnfkU3MNwMOcXNY+AiI5xd1tYJs24/qxsbM4ZnwWPn6d9PL3aBgjqw66yS3cjYFT+qmNn2DdQBHbsQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715148283; c=relaxed/simple; bh=zR/J/GQwZZOwdR5Vz+cQ0vtwUaYOtxxQWeQiJU7jJl8=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=nb1v7kEUgpmYmS/kO1mNRrWMjuOxjVCAO+PilJ/+v4Cil8+FYEcHiQDtYBQmdWoAbbZn8HWC9RWHuax4wRZBzMzDi0KzxmyoX8vzJGB6/MQ1OVO7tYZahaWuB7Hzipxse4nz7eocSjis/BAA+7cdWIylS9K3htVPuzrx5WHHSsM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=lEyLfjgH; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="lEyLfjgH" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 17A71C113CC; Wed, 8 May 2024 06:04:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1715148283; bh=zR/J/GQwZZOwdR5Vz+cQ0vtwUaYOtxxQWeQiJU7jJl8=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=lEyLfjgHyL2A7vdOPnsomxYbOvpKv/cJ3ra/IoyPzYtBJnxcTixj5RH53wrata6eG k9pgiAw2wVFcwsMT8/1qnRqGyFCtd/mVCB7HrLb4Dy7P5WpP8QskfIS+PLQcjXWzak x7BwcQkRcMfONWXml58inDjrBpRDwxZ/DvhirZs9SAdEDR3UiltAEK85vgHHNuPEsb OKLe4bHZItqLk63gWEHjR7R9IoMDYhBKQxjNg2wtnmWeWd62QLnMf+65SvPF/GFOB1 MmHonyjeWu5Uap7LAMjIalcDyE0WZMVgcrF2RT030TIAxEuubH8oraVCQbUcGqN1mB Tj8PuATo4dXsA== Received: from cpe.ge-3-3-8-100.vbrnqe11.dk.customer.tdc.net ([80.164.103.190] helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1s4aPw-00BWru-6v; Wed, 08 May 2024 07:04:40 +0100 Date: Wed, 08 May 2024 07:04:34 +0100 Message-ID: <87ikzozvnx.wl-maz@kernel.org> From: Marc Zyngier To: Will Deacon Cc: kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Suzuki K Poulose , Oliver Upton , Zenghui Yu Subject: Re: [PATCH] KVM: arm64: Correct BTYPE/SS in host SMC emulation In-Reply-To: <20240507145733.GB22453@willie-the-truck> References: <20240502180020.3215547-1-maz@kernel.org> <20240507145733.GB22453@willie-the-truck> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 80.164.103.190 X-SA-Exim-Rcpt-To: will@kernel.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, james.morse@arm.com, suzuki.poulose@arm.com, oliver.upton@linux.dev, yuzenghui@huawei.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Tue, 07 May 2024 15:57:34 +0100, Will Deacon wrote: > > On Thu, May 02, 2024 at 07:00:20PM +0100, Marc Zyngier wrote: > > When taking a trap for an SMC instruction on the host, we must > > stau true to the letter of the architecture and perform all the > > typo: stay > > > actions that the CPU would otherwise do. Among those are clearing > > the BTYPE and SS bits. > > > > Just do that. > > > > Fixes: a805e1fb3099 ("KVM: arm64: Add SMC handler in nVHE EL2") > > Signed-off-by: Marc Zyngier > > --- > > arch/arm64/kvm/hyp/include/hyp/adjust_pc.h | 6 ++++++ > > 1 file changed, 6 insertions(+) > > > > diff --git a/arch/arm64/kvm/hyp/include/hyp/adjust_pc.h b/arch/arm64/kvm/hyp/include/hyp/adjust_pc.h > > index 4fdfeabefeb4..b1afb7b59a31 100644 > > --- a/arch/arm64/kvm/hyp/include/hyp/adjust_pc.h > > +++ b/arch/arm64/kvm/hyp/include/hyp/adjust_pc.h > > @@ -47,7 +47,13 @@ static inline void __kvm_skip_instr(struct kvm_vcpu *vcpu) > > */ > > static inline void kvm_skip_host_instr(void) > > { > > + u64 spsr = read_sysreg_el2(SYS_SPSR); > > + > > write_sysreg_el2(read_sysreg_el2(SYS_ELR) + 4, SYS_ELR); > > + > > + spsr &= ~(PSR_BTYPE_MASK | DBG_SPSR_SS); > > + > > + write_sysreg_el2(spsr, SYS_SPSR); > > The handling of SS looks correct to me, but I think the BTYPE > manipulation could do with a little more commentary as it looks quite > subtle when the SMC is in a guarded page. Am I right in thinking: > > * If the SMC is in a guarded page, the Branch Target exception is > higher priority (12) than the trap to EL2 and so the host will > handle it. > > * Therefore if a trapping SMC is in a guarded page, BTYPE must be > zero and we don't have to worry about injecting a Branch Target > exception. > > * Otherwise, if the SMC is in a non-guarded page, we should clear it > to 0 per the architecture (R_YWFHD). > > ? This is all correct. If we get to emulate the SMC by trapping to EL2, it is that the instruction already satisfied the more basic execution requirements such as having an acceptable BTYPE at that PC. If that's OK with you, I'll nick that write-up and stick it into the next revision of the patch. > Having said that, I can't actually find the priority of an SMC trapped > to EL2 by HCR_EL2.TSC in the Arm ARM. Trapped HVCs are priority 15 and > SMCs trapped to EL3 are priority 23. My understanding is that this falls into the catch-all priority 22 of R_ZFGJP ("Other than an exception defined by priorities 4-21 inclusive, any exception that is the result of a configurable access to instructions, where the exception is taken to EL2."). Thanks, M. -- Without deviation from the norm, progress is not possible.