From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C02ECAD59; Sat, 1 Jun 2024 10:24:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717237492; cv=none; b=aECX3L3eo/sytDY2wTvTgC7SiROf8Zh5NdAuyJtGpVVpiDS29/rEXmh283nm9v9eiKZjhqmgeEaCGKXVfMQAp/+Yprz1zMZxqvIj9N2+RVgOmubPWL8K1T/Mdm6J8Ss3VD2B1ZD3TTA010wC8B2mgcnBn7lSLvCHzRqmR6m1OQY= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717237492; c=relaxed/simple; bh=2bLc5BemzdRY0odLxllEa8Oj/5o5CSdq65VCuf7cwSo=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=hSZH8CU+EKd+/P6EbQoUMCPEDbUUqIG2YSbAwvrrUgvuxpYVrQvI+kI9xNtWQQ2p447qRsgbMX/uFsrMdvtShrYb2PxqbabXQlB6qkoe4bCvA05OGgZhUIS82Bl8ML+JgjZbzPax/diaJVi/LDAvOI1AVpfozdSjcGAfWxr97Hg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=JoF/Lvb7; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="JoF/Lvb7" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 51A1AC116B1; Sat, 1 Jun 2024 10:24:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1717237492; bh=2bLc5BemzdRY0odLxllEa8Oj/5o5CSdq65VCuf7cwSo=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=JoF/Lvb7omn8vrNETem+oO0Z9OAEdtp5gVVU1c+nfR2+NZ+424QQajWy6ZK5XmsAa M1rRvhA3db8vrqD6/pVtPF4v70Xh/H6lVTzJBP7RvDqq9t6KyfrxZACttwUd5gCT/d PMqfqk/LDKP4i47TFN8EjrFdfdDBrvkbQzwAP+ZrZKK2Qev54ZcOD4/ZoKkhfCPAks LaZ7Vx7maeWdjGW6a0eRlJtM8x7bcVp2lpMRVGR3R9X6X9ZtqCFMw0znoe/VJbrXw0 LqF88JQsWjo4WWAElhy1pAra4fXbdIuhwDDf7hayJPvEO/Bd24Ho/Fng3Q5jDwlM6T V5VMpkmV7xHrA== Received: from sofa.misterjones.org ([185.219.108.64] helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1sDLus-00HO1S-AQ; Sat, 01 Jun 2024 11:24:50 +0100 Date: Sat, 01 Jun 2024 11:24:49 +0100 Message-ID: <87jzj92c5q.wl-maz@kernel.org> From: Marc Zyngier To: Oliver Upton Cc: kvmarm@lists.linux.dev, James Morse , Suzuki K Poulose , Zenghui Yu , kvm@vger.kernel.org Subject: Re: [PATCH 00/11] KVM: arm64: nv: FPSIMD/SVE support In-Reply-To: <20240531231358.1000039-1-oliver.upton@linux.dev> References: <20240531231358.1000039-1-oliver.upton@linux.dev> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: oliver.upton@linux.dev, kvmarm@lists.linux.dev, james.morse@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, kvm@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Sat, 01 Jun 2024 00:13:47 +0100, Oliver Upton wrote: > > Hey! > > I've decided to start messing around with nested and have SVE support > working for a nested guest. For the sake of landing a semi-complete > feature upstream, I've also picked up the FPSIMD patches from the NV > series Marc is carrying. > > The most annoying part about this series (IMO) is that ZCR_EL2 traps > behave differently from what needs to be virtualized for the guest when > HCR_EL2.NV = 1, as it takes a sysreg trap (EC = 0x18) instead of an SVE > trap (EC = 0x19). So, we need to synthesize the ESR value when > reflecting back into the guest hypervisor. That's unfortunately not a unique case. The ERETAx emulation already requires us to synthesise the ESR on PAC check failure, and I'm afraid ZCR_EL2 might not be the last case. In general, we'll see this problem for any instruction or sysreg that can generate multiple exception classes. > > Otherwise, some care is required to slap the guest hypervisor's ZCR_EL2 > into the right place depending on whether or not the vCPU is in a hyp > context, since it affects the hyp's usage of SVE in addition to the VM. > > There's more work to be done for honoring the L1's CPTR traps, as this > series only focuses on getting SVE and FPSIMD traps right. We'll get > there one day. I have patches for that in my NV series, which would take the place of patches 9 and 10 in your series (or supplement them, depending on how we want to slice this). > > I tested this using a mix of the fpsimd-test and sve-test selftests > running at L0, L1, and L2 concurrently on Neoverse V2. Thanks a lot for tackling this. It'd be good to put together a series that has the EL2 sysreg save/restore patches as a prefix of this, plus the CPTR_EL2 changes. That way, we'd have something that can be merged as a consistent set. I'll try to take this into my branch and see what explodes! Cheers, M. -- Without deviation from the norm, progress is not possible.