From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5A229C43334 for ; Fri, 1 Jul 2022 15:05:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231295AbiGAPFS (ORCPT ); Fri, 1 Jul 2022 11:05:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34890 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231146AbiGAPFQ (ORCPT ); Fri, 1 Jul 2022 11:05:16 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 82A65E5E for ; Fri, 1 Jul 2022 08:05:15 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id EAB5F6237C for ; Fri, 1 Jul 2022 15:05:14 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 54900C341C7; Fri, 1 Jul 2022 15:05:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1656687914; bh=luePMy/Z+vkn4tLOUBGSHwehJjCg/Kb2+oybCvWuF1Q=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=oOg1vwjG3G7T2Wf6Yg0tfnRzbcsGEsL1VRRCS4vw7a9IrVMLCtDqGRRwq5nBE6XJk 1+qrO6BtgN27sFzj6qKIkj1IswexowtASGeDvf/jnR5pTHoWHxfIuIk/ibSwPeW1QP rlB+FThsYCqOP0Rmv+7vNx+YJv+9qANfXtZE3wu8RMMzku5BztMFpzuQ0F02FErU+q /xtikYv7xZc+GjgX/T+VZAkh0vQqpdp58DO7tcGcLoKiSsDCM238HEuAquwx5TqXs4 526sMNwkxOsMLypRu6pFCht0kIF4Jyc5rkv77o5t2fLsiUOReGsTdofZSW8/q1xK1i cfPdMvHFdICQQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1o7ICm-004caJ-0a; Fri, 01 Jul 2022 16:05:12 +0100 Date: Fri, 01 Jul 2022 16:05:11 +0100 Message-ID: <87k08w27rs.wl-maz@kernel.org> From: Marc Zyngier To: Andre Przywara Cc: Will Deacon , Julien Thierry , Alexandru Elisei , kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org Subject: Re: [PATCH kvmtool] arm: gic: fdt: fix PPI CPU mask calculation In-Reply-To: <20220616145526.3337196-1-andre.przywara@arm.com> References: <20220616145526.3337196-1-andre.przywara@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: andre.przywara@arm.com, will@kernel.org, julien.thierry.kdev@gmail.com, alexandru.elisei@arm.com, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On Thu, 16 Jun 2022 15:55:26 +0100, Andre Przywara wrote: > > The GICv2 DT binding describes the third cell in each interrupt > descriptor as holding the trigger type, but also the CPU mask that this > IRQ applies to, in bits [15:8]. However this is not the case for GICv3, > where we don't use a CPU mask in the third cell: a simple mask wouldn't > fit for the many more supported cores anyway. > > At the moment we fill this CPU mask field regardless of the GIC type, > for the PMU and arch timer DT nodes. This is not only the wrong thing to > do in case of a GICv3, but also triggers UBSAN splats when using more > than 30 cores, as we do shifting beyond what a u32 can hold: > $ lkvm run -k Image -c 31 --pmu > arm/timer.c:13:22: runtime error: left shift of 1 by 31 places cannot be represented in type 'int' > arm/timer.c:13:38: runtime error: signed integer overflow: -2147483648 - 1 cannot be represented in type 'int' > arm/timer.c:13:43: runtime error: left shift of 2147483647 by 8 places cannot be represented in type 'int' > arm/aarch64/pmu.c:202:22: runtime error: left shift of 1 by 31 places cannot be represented in type 'int' > arm/aarch64/pmu.c:202:38: runtime error: signed integer overflow: -2147483648 - 1 cannot be represented in type 'int' > arm/aarch64/pmu.c:202:43: runtime error: left shift of 2147483647 by 8 places cannot be represented in type 'int' > > Fix that by adding a function that creates the mask by looking at the > GIC type first, and returning zero when a GICv3 is used. Also we > explicitly check for the CPU limit again, even though this would be > done before already, when we try to create a GICv2 VM with more than 8 > cores. > > Signed-off-by: Andre Przywara Acked-by: Marc Zyngier M. -- Without deviation from the norm, progress is not possible.