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Mon, 13 Jul 2020 15:20:33 +0100 Date: Mon, 13 Jul 2020 15:20:31 +0100 Message-ID: <87o8ojxzrk.wl-maz@kernel.org> From: Marc Zyngier To: Andrew Scull Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, Andre Przywara , Christoffer Dall , Dave Martin , Jintack Lim , Alexandru Elisei , George Cherian , "Zengtao (B)" , Will Deacon , Catalin Marinas , Mark Rutland , James Morse , Julien Thierry , Suzuki K Poulose , kernel-team@android.com Subject: Re: [PATCH v2 01/17] KVM: arm64: Factor out stage 2 page table data from struct kvm In-Reply-To: <20200713094749.GA1705612@google.com> References: <20200615132719.1932408-1-maz@kernel.org> <20200615132719.1932408-2-maz@kernel.org> <20200713094749.GA1705612@google.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL/10.8 EasyPG/1.0.0 Emacs/26.3 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: ascull@google.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, andre.przywara@arm.com, christoffer.dall@arm.com, Dave.Martin@arm.com, jintack@cs.columbia.edu, alexandru.elisei@arm.com, gcherian@marvell.com, prime.zeng@hisilicon.com, will@kernel.org, catalin.marinas@arm.com, mark.rutland@arm.com, james.morse@arm.com, julien.thierry.kdev@gmail.com, suzuki.poulose@arm.com, kernel-team@android.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On Mon, 13 Jul 2020 10:47:49 +0100, Andrew Scull wrote: >=20 > On Mon, Jun 15, 2020 at 02:27:03PM +0100, Marc Zyngier wrote: > > -static void __hyp_text __tlb_switch_to_guest_nvhe(struct kvm *kvm, > > +static void __hyp_text __tlb_switch_to_guest_nvhe(struct kvm_s2_mmu *m= mu, > > struct tlb_inv_context *cxt) > > { > > if (cpus_have_final_cap(ARM64_WORKAROUND_SPECULATIVE_AT)) { > > @@ -79,22 +79,19 @@ static void __hyp_text __tlb_switch_to_guest_nvhe(s= truct kvm *kvm, > > isb(); > > } > > =20 > > - /* __load_guest_stage2() includes an ISB for the workaround. */ > > - __load_guest_stage2(kvm); > > - asm(ALTERNATIVE("isb", "nop", ARM64_WORKAROUND_SPECULATIVE_AT)); > > + __load_guest_stage2(mmu); > > } >=20 > Just noticed that this drops the ISB when the speculative AT workaround > is not active. >=20 > This alternative is 'backwards' to avoid a double ISB as there is one in > __load_guest_stage2 when the workaround is active. I hope to address > this smell in an upcoming series but, for now, we should at least have > an ISB. Indeed. I must have messed up a conflict resolution here. I'll stick this fix on top. Thanks, M. =46rom 997c17ffe879dcad40b49a0c844c39f5d071dee9 Mon Sep 17 00:00:00 2001 From: Marc Zyngier Date: Mon, 13 Jul 2020 15:15:14 +0100 Subject: [PATCH] KVM: arm64: Restore missing ISB on nVHE __tlb_switch_to_gu= est Commit a0e50aa3f4a8 ("KVM: arm64: Factor out stage 2 page table data from struct kvm") dropped the ISB after __load_guest_stage2(), only leaving the one that is required when the speculative AT workaround is in effect. As Andrew points it: "This alternative is 'backwards' to avoid a double ISB as there is one in __load_guest_stage2 when the workaround is active." Restore the missing ISB, conditionned on the AT workaround not being active. Fixes: a0e50aa3f4a8 ("KVM: arm64: Factor out stage 2 page table data from s= truct kvm") Reported-by: Andrew Scull Signed-off-by: Marc Zyngier --- arch/arm64/kvm/hyp/nvhe/tlb.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/kvm/hyp/nvhe/tlb.c b/arch/arm64/kvm/hyp/nvhe/tlb.c index 69eae608d670..f31185272b50 100644 --- a/arch/arm64/kvm/hyp/nvhe/tlb.c +++ b/arch/arm64/kvm/hyp/nvhe/tlb.c @@ -31,7 +31,9 @@ static void __tlb_switch_to_guest(struct kvm_s2_mmu *mmu, isb(); } =20 + /* __load_guest_stage2() includes an ISB for the workaround. */ __load_guest_stage2(mmu); + asm(ALTERNATIVE("isb", "nop", ARM64_WORKAROUND_SPECULATIVE_AT)); } =20 static void __tlb_switch_to_host(struct tlb_inv_context *cxt) --=20 2.27.0 --=20 Without deviation from the norm, progress is not possible.