From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
To: Alexander Graf <agraf@suse.de>
Cc: kvm-ppc@vger.kernel.org, kvm@vger.kernel.org
Subject: Re: [PATCH 0/6] KVM: PPC: Book3S PR: Add POWER8 support
Date: Mon, 05 May 2014 20:08:45 +0530 [thread overview]
Message-ID: <87oazc9toq.fsf@linux.vnet.ibm.com> (raw)
In-Reply-To: <5367737B.1000100@suse.de>
Alexander Graf <agraf@suse.de> writes:
> On 05/04/2014 06:36 PM, Aneesh Kumar K.V wrote:
>> Alexander Graf <agraf@suse.de> writes:
>>
>>> When running on a POWER8 host, we get away with running the guest as POWER7
>>> and nothing falls apart.
>>>
>>> However, when we start exposing POWER8 as guest CPU, guests will start using
>>> new abilities on POWER8 which we need to handle.
>>>
>>> This patch set does a minimalistic approach to implementing those bits to
>>> make guests happy enough to run.
>>>
>>>
>>> Alex
>>>
>>> Alexander Graf (6):
>>> KVM: PPC: Book3S PR: Ignore PMU SPRs
>>> KVM: PPC: Book3S PR: Emulate TIR register
>>> KVM: PPC: Book3S PR: Handle Facility interrupt and FSCR
>>> KVM: PPC: Book3S PR: Expose TAR facility to guest
>>> KVM: PPC: Book3S PR: Expose EBB registers
>>> KVM: PPC: Book3S PR: Expose TM registers
>>>
>>> arch/powerpc/include/asm/kvm_asm.h | 18 ++++---
>>> arch/powerpc/include/asm/kvm_book3s_asm.h | 2 +
>>> arch/powerpc/include/asm/kvm_host.h | 3 ++
>>> arch/powerpc/kernel/asm-offsets.c | 3 ++
>>> arch/powerpc/kvm/book3s.c | 34 +++++++++++++
>>> arch/powerpc/kvm/book3s_emulate.c | 53 ++++++++++++++++++++
>>> arch/powerpc/kvm/book3s_hv.c | 30 -----------
>>> arch/powerpc/kvm/book3s_pr.c | 82 +++++++++++++++++++++++++++++++
>>> arch/powerpc/kvm/book3s_segment.S | 25 ++++++++++
>>> 9 files changed, 212 insertions(+), 38 deletions(-)
>>>
>> I did most of this as part of
>>
>> [RFC PATCH 01/10] KVM: PPC: BOOK3S: PR: Add POWER8 support
>> http://mid.gmane.org/1390927455-3312-1-git-send-email-aneesh.kumar@linux.vnet.ibm.com
>>
>> Any reason why that is not picked up ? TM was the reason I didn't push the
>> patchset again. I was not sure how to get all the TM details to
>> work.
>
> Ugh, I guess I mostly discarded it as brainstorm patches because they
> were marked RFC :(
>
Do you want me to rework them ?. I guess facility unavailable part and
TM part in this series are better than what I had. Rest all are more or
less similar. Or you could cherry pick the SPR handling you haven't
added yet from this series ?
-aneesh
next prev parent reply other threads:[~2014-05-05 14:38 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-04-29 16:17 [PATCH 0/6] KVM: PPC: Book3S PR: Add POWER8 support Alexander Graf
2014-04-29 16:17 ` [PATCH 1/6] KVM: PPC: Book3S PR: Ignore PMU SPRs Alexander Graf
2014-04-30 22:12 ` Paul Mackerras
2014-05-02 8:35 ` Alexander Graf
2014-05-07 7:09 ` Paul Mackerras
2014-05-08 12:11 ` Alexander Graf
2014-04-29 16:17 ` [PATCH 2/6] KVM: PPC: Book3S PR: Emulate TIR register Alexander Graf
2014-04-30 5:51 ` Michael Neuling
2014-04-30 10:06 ` Alexander Graf
2014-04-29 16:17 ` [PATCH 3/6] KVM: PPC: Book3S PR: Handle Facility interrupt and FSCR Alexander Graf
2014-04-29 16:17 ` [PATCH 4/6] KVM: PPC: Book3S PR: Expose TAR facility to guest Alexander Graf
2014-04-29 16:17 ` [PATCH 5/6] KVM: PPC: Book3S PR: Expose EBB registers Alexander Graf
2014-04-29 16:17 ` [PATCH 6/6] KVM: PPC: Book3S PR: Expose TM registers Alexander Graf
2014-05-17 6:20 ` Paul Mackerras
2014-05-19 13:09 ` Alexander Graf
2014-05-20 9:59 ` Paul Mackerras
2014-05-20 11:49 ` Alexander Graf
2014-05-04 16:36 ` [PATCH 0/6] KVM: PPC: Book3S PR: Add POWER8 support Aneesh Kumar K.V
2014-05-05 11:18 ` Alexander Graf
2014-05-05 14:38 ` Aneesh Kumar K.V [this message]
2014-05-05 14:42 ` Alexander Graf
2014-05-05 14:48 ` Aneesh Kumar K.V
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