Re: [RFC v2 01/17] x86/apic: Add new driver for Secure AVIC

Neeraj Upadhyay
2025-04-01T05:12:32Z

On 3/21/2025 10:41 PM, Borislav Petkov wrote:
> On Fri, Mar 21, 2025 at 09:39:22PM +0530, Neeraj Upadhyay wrote:
>> Ok, something like below?
>
> Or something like that:
>
> diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
> index 76b16a2b03ee..1a5fa10ee4b9 100644
> --- a/arch/x86/Kconfig
> +++ b/arch/x86/Kconfig
> @@ -476,7 +476,7 @@ config X86_X2APIC
>
> config AMD_SECURE_AVIC
> bool "AMD Secure AVIC"
> - depends on X86_X2APIC
> + depends on AMD_MEM_ENCRYPT && X86_X2APIC
> help
> This enables AMD Secure AVIC support on guests that have this feature.
>
> @@ -1517,7 +1517,6 @@ config AMD_MEM_ENCRYPT
> select X86_MEM_ENCRYPT
> select UNACCEPTED_MEMORY
> select CRYPTO_LIB_AESGCM
> - select AMD_SECURE_AVIC
> help
> Say yes to enable support for the encryption of system memory.
> This requires an AMD processor that supports Secure Memory
> diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
> index edc31615cb67..ecf86b8a6601 100644
> --- a/arch/x86/include/asm/msr-index.h
> +++ b/arch/x86/include/asm/msr-index.h
> @@ -685,8 +685,14 @@
> #define MSR_AMD64_SNP_VMSA_REG_PROT BIT_ULL(MSR_AMD64_SNP_VMSA_REG_PROT_BIT)
> #define MSR_AMD64_SNP_SMT_PROT_BIT 17
> #define MSR_AMD64_SNP_SMT_PROT BIT_ULL(MSR_AMD64_SNP_SMT_PROT_BIT)
> +
> #define MSR_AMD64_SNP_SECURE_AVIC_BIT 18
> -#define MSR_AMD64_SNP_SECURE_AVIC BIT_ULL(MSR_AMD64_SNP_SECURE_AVIC_BIT)
> +#ifdef CONFIG_AMD_SECURE_AVIC
> +#define MSR_AMD64_SNP_SECURE_AVIC BIT_ULL(MSR_AMD64_SNP_SECURE_AVIC_BIT)
> +#else
> +#define MSR_AMD64_SNP_SECURE_AVIC 0
> +#endif
> +

I missed this part. I think this does not work because if CONFIG_AMD_SECURE_AVIC
is not enabled, MSR_AMD64_SNP_SECURE_AVIC bit becomes 0 in both SNP_FEATURES_IMPL_REQ
and SNP_FEATURES_PRESENT.

So, snp_get_unsupported_features() won't report SECURE_AVIC feature as not being
enabled in guest launched with SECURE_AVIC vmsa feature enabled. Thoughts?

u64 snp_get_unsupported_features(u64 status)
{
if (!(status & MSR_AMD64_SEV_SNP_ENABLED))
return 0;

return status & SNP_FEATURES_IMPL_REQ & ~SNP_FEATURES_PRESENT;
}

- Neeraj

> #define MSR_AMD64_SNP_RESV_BIT 19
> #define MSR_AMD64_SNP_RESERVED_MASK GENMASK_ULL(63, MSR_AMD64_SNP_RESV_BIT)
> #define MSR_AMD64_RMP_BASE 0xc0010132
>