From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 38BC8258EEF; Sun, 21 Sep 2025 11:00:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758452418; cv=none; b=Ijzk0KXlj6x4CTLnpZe2GLsgrkoruOiYogau8TJwHiRs6SrS/Ru1m/D9Y2YQW6+dcScTeCgzG/rQJBBE9lUaiOlemmq9F8XMmIEHdAaha43RGNhbG4uada3LuOjB8MXNhP0uOXx8yDlMpwc2OiIeHLfk3kl2aA6i1VnHwVsOuDQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758452418; c=relaxed/simple; bh=mcaq5UETXQW68M5Km24IAUwTvGYTX4atFsOueMZbGpQ=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=Cq+NvJD9G95LxBEHTjPPS2bL/o5QKMcYWiCC7IVb58Ajn5VXtr3qZwRvN6AhWQteeAbv9gmwvLPtaqMUlHeP/wF2I30WmAMbF5Z0/1iFlrQ5CT2+BU6D2FLWGE53Grq69rkwScyvgsn6NjHKr06Rxof02fIfmpt2ZSwgr8Un6cQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=udS1F2yS; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="udS1F2yS" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 058E1C4CEE7; Sun, 21 Sep 2025 11:00:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1758452418; bh=mcaq5UETXQW68M5Km24IAUwTvGYTX4atFsOueMZbGpQ=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=udS1F2ySB4D8hkXwlAnHvYzFs1zz9juYY2mg1t4Bcy+yhN/y5aX4eSJ7cpucxJ2bc Hznv42AbObEd+C1mT5o5y2zay5l0aF7O7HhsJnz+50h3GRKAX1EUrDPWCZC7G9AA1J Cg/jYG40bRQhECniBPcjrSQF6nxUfPeljMfwQ/Vyc1RChyCo8f/H6G9SsTWdFisVSj VoV3iu8SsDPbdjAg/IRFFqxXdQSpvlQ+UiTeOaRxY6isjaP+UO454UzII5bOPq4V/a J21lI0uGTKhw8HNvXbxDuGDWxH8CqadGI67F+A1iL4xemKoSCdQztH+9T31wB9TicV ouX6UPdtBnS2g== Received: from sofa.misterjones.org ([185.219.108.64] helo=lobster-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1v0Hnj-000000089ti-2vFR; Sun, 21 Sep 2025 11:00:15 +0000 Date: Sun, 21 Sep 2025 12:00:15 +0100 Message-ID: <87qzw0xe80.wl-maz@kernel.org> From: Marc Zyngier To: Oliver Upton Cc: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, Joey Gouly , Suzuki K Poulose , Zenghui Yu Subject: Re: [PATCH v2 00/16] KVM: arm64: TTW reporting on SEA and 52bit PA in S1 PTW In-Reply-To: References: <20250915114451.660351-1-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: oliver.upton@linux.dev, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Fri, 19 Sep 2025 23:37:15 +0100, Oliver Upton wrote: > > On Mon, Sep 15, 2025 at 12:44:35PM +0100, Marc Zyngier wrote: > > Yes, $SUBJECT rolls off the tongue. > > > > This series was triggered by the realisation that when injecting an > > SEA while on a S1PTW fault, we don't report the level of the walk and > > instead give a bare SEA, which definitely violates the architecture. > > > > This state of things dates back to the pre-NV days, when we didn't > > have a S1 page table walker, and really didn't want to implement one. > > I've since moved on and reluctantly implemented one, which means we > > now *could* provide the level if we really wanted to. > > > > However, nothing is that simple. The current code in at.c is firmly > > 48bit, as our NV implementation doesn't yet support 52bit PA, while an > > EL1 VM can happily enjoy LPA and LPA2. As a result, it is necessary to > > expand the S1 PTW to support both LPA and LPA2. Joy. > > > > Then, once the above is achieved, we need to hook into the PTW > > machinery to match the first level of the walk that results in > > accessing the faulty address. For this, we introduce a simple filter > > mechanism that could be expanded if we needed to (no, please no). > > > > Finally, we can plug this into the fault injection path, and enjoy > > seeing the translation level being populated in the ESR_ELx register. > > > > Patches on top of 6.16-rc4. I intend to take this into 6.18, so shout > > if you don't like the idea! > > Just some minor gripes, otherwise this LGTM. > > Reviewed-by: Oliver Upton Thanks for spending the time reviewing it and spotting some crucial mistakes. I've applied your suggestions and pushed out the result, which should be in the next -next. M. -- Jazz isn't dead. It just smells funny.