From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A7722C6FD18 for ; Wed, 29 Mar 2023 07:34:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230150AbjC2He3 (ORCPT ); Wed, 29 Mar 2023 03:34:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41284 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229729AbjC2HeC (ORCPT ); Wed, 29 Mar 2023 03:34:02 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9346B35B3 for ; Wed, 29 Mar 2023 00:31:33 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id DCB8D60C5B for ; Wed, 29 Mar 2023 07:31:30 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 47D39C433EF; Wed, 29 Mar 2023 07:31:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1680075090; bh=IsuvjwQiGQfvNNZi00ZhmP672wnDWL3sVGtWAk43ClI=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=c0FvRHNYpHq7NWB2/Tpo6+WePRmcTBjwjGK+bIu14Ojeo4eHotMh6rkeOo1xy6TvV V+tmmCcL8aqbOh9YJ94MxDdRk8h7DuxqwJIEsEJL4P7QUv5YIndE8f1k5XLNlN+c0t xPRhM/aqU4b9WblgYgQaZMEtDvZA+GapOrRT0Cwqb3Oyv4zihZdoFbTeiBxE5WyK9Z XCTjzbe6mvmWviHFDGhI2HFjmaiduMUEHhwrd1g1rVtdCRLCLnIAAhemTpD3Xg4UWw Q+95qU5N5X7aaawzPtpo0HGW6ZGT1SVFzKR8nDO9BJ3WJ/kpUBJ4y56qI/ov7uiUbq MCVQaACcaKS3w== Received: from [82.132.185.251] (helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1phQHH-003yn1-I3; Wed, 29 Mar 2023 08:31:27 +0100 Date: Wed, 29 Mar 2023 08:31:24 +0100 Message-ID: <87v8ikqaib.wl-maz@kernel.org> From: Marc Zyngier To: Reiji Watanabe Cc: Oliver Upton , kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Zenghui Yu , Suzuki K Poulose , Paolo Bonzini , Ricardo Koller , Jing Zhang , Raghavendra Rao Anata , Will Deacon Subject: Re: [PATCH v1 1/2] KVM: arm64: PMU: Restore the host's PMUSERENR_EL0 In-Reply-To: <20230329002136.2463442-2-reijiw@google.com> References: <20230329002136.2463442-1-reijiw@google.com> <20230329002136.2463442-2-reijiw@google.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 82.132.185.251 X-SA-Exim-Rcpt-To: reijiw@google.com, oliver.upton@linux.dev, kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, james.morse@arm.com, alexandru.elisei@arm.com, yuzenghui@huawei.com, suzuki.poulose@arm.com, pbonzini@redhat.com, ricarkol@google.com, jingzhangos@google.com, rananta@google.com, will@kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On Wed, 29 Mar 2023 01:21:35 +0100, Reiji Watanabe wrote: > > Restore the host's PMUSERENR_EL0 value instead of clearing it, > before returning back to userspace, as the host's EL0 might have > a direct access to PMU registers (some bits of PMUSERENR_EL0 > might not be zero). > > Fixes: 83a7a4d643d3 ("arm64: perf: Enable PMU counter userspace access for perf event") > Signed-off-by: Reiji Watanabe > --- > arch/arm64/include/asm/kvm_host.h | 3 +++ > arch/arm64/kvm/hyp/include/hyp/switch.h | 3 ++- > 2 files changed, 5 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h > index bcd774d74f34..82220ecec10e 100644 > --- a/arch/arm64/include/asm/kvm_host.h > +++ b/arch/arm64/include/asm/kvm_host.h > @@ -544,6 +544,9 @@ struct kvm_vcpu_arch { > > /* Per-vcpu CCSIDR override or NULL */ > u32 *ccsidr; > + > + /* the value of host's pmuserenr_el0 before guest entry */ > + u64 host_pmuserenr_el0; I don't think we need this in each and every vcpu. Why can't this be placed in struct kvm_host_data and accessed via the per-cpu pointer? Maybe even use the PMUSERNR_EL0 field in the sysreg array? There is probably a number of things that we could move there, but let's start by not adding more unnecessary stuff to the vcpu structure. > }; > > /* > diff --git a/arch/arm64/kvm/hyp/include/hyp/switch.h b/arch/arm64/kvm/hyp/include/hyp/switch.h > index 07d37ff88a3f..44b84fbdde0d 100644 > --- a/arch/arm64/kvm/hyp/include/hyp/switch.h > +++ b/arch/arm64/kvm/hyp/include/hyp/switch.h > @@ -82,6 +82,7 @@ static inline void __activate_traps_common(struct kvm_vcpu *vcpu) > */ > if (kvm_arm_support_pmu_v3()) { > write_sysreg(0, pmselr_el0); > + vcpu->arch.host_pmuserenr_el0 = read_sysreg(pmuserenr_el0); > write_sysreg(ARMV8_PMU_USERENR_MASK, pmuserenr_el0); > } > > @@ -106,7 +107,7 @@ static inline void __deactivate_traps_common(struct kvm_vcpu *vcpu) > > write_sysreg(0, hstr_el2); > if (kvm_arm_support_pmu_v3()) > - write_sysreg(0, pmuserenr_el0); > + write_sysreg(vcpu->arch.host_pmuserenr_el0, pmuserenr_el0); > > if (cpus_have_final_cap(ARM64_SME)) { > sysreg_clear_set_s(SYS_HFGRTR_EL2, 0, Thanks, M. -- Without deviation from the norm, progress is not possible.