Re: [PATCH v16 11/11] docs/s390x/cpu topology: document s390x cpu topology

Pierre Morel
2023-02-27T17:34:55Z

On 2/27/23 15:27, Thomas Huth wrote:
> On 27/02/2023 15.17, Pierre Morel wrote:
>>
>> On 2/27/23 14:58, Thomas Huth wrote:
>>> On 22/02/2023 15.21, Pierre Morel wrote:
>>>> Add some basic examples for the definition of cpu topology
>>>> in s390x.
>>>>
>>>> Signed-off-by: Pierre Morel <pmorel@linux.ibm.com>
>>>> ---
>>>>   docs/system/s390x/cpu-topology.rst | 378
>>>> +++++++++++++++++++++++++++++
>>>>   docs/system/target-s390x.rst       |   1 +
>>>>   2 files changed, 379 insertions(+)
>>>>   create mode 100644 docs/system/s390x/cpu-topology.rst
>>>>
>>>> diff --git a/docs/system/s390x/cpu-topology.rst
>>>> b/docs/system/s390x/cpu-topology.rst
>>>> new file mode 100644
>>>> index 0000000000..d470e28b97
>>>> --- /dev/null
>>>> +++ b/docs/system/s390x/cpu-topology.rst
>>>> @@ -0,0 +1,378 @@
>>>> +CPU topology on s390x
>>>> +=====================
>>>> +
>>>> +Since QEMU 8.0, CPU topology on s390x provides up to 3 levels of
>>>> +topology containers: drawers, books, sockets, defining a tree shaped
>>>> +hierarchy.
>>>> +
>>>> +The socket container contains one or more CPU entries consisting
>>>> +of a bitmap of three dentical CPU attributes:
>>>
>>> What do you mean by "dentical" here?
>>
>> :D i.. dentical
>>
>> I change it to identical
>
> Ok, but even with "i" at the beginning, it does not make too much
> sense here to me - I'd interpret "identical" as "same", but these
> attributes have clearly different meanings, haven't they?
>
>  Thomas
>
>
Ah OK I understand what is unclear.

What I mean is that in each socket we have several CPU TLE entries each
entry has different attributes values and contains CPU bit in the mask
for CPU with identical attributes.

For example,

in the case of horizontal polarization, we have one CPU TLE entry for
low entitlement, one CPU TLE for medium entitlement, one for high
entitlement and one for high entitlement with dedicated CPU

in the case of horizontal polarization we have one CPU TLE for non
dedicated CPU and one for dedicated CPU.

Only CPU TLE with at least one bit (CPU) set in the mask is written
inside the SYSIB.

Regards,

Pierre