From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="kIlh4/LD"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="uKMrxTVR" Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F1937135; Wed, 6 Dec 2023 12:44:04 -0800 (PST) From: Thomas Gleixner DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1701895443; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=tt/d27mY59C3uUO6MUg2plSSXPKh9R05K6pzapnG0gA=; b=kIlh4/LDNh8d4Kj8mF2tshqjkGW8VUg6IY6TQZALVmfSU1bOYfxNCFkPNET+IL3SuoCHK7 38cFzSwsoTIpPnaj2XHCvqHMpqZd25mTW7oDvJARAvwjU86YavzyZEAtxpG+ucN4kfMQW3 87wk/GrPJnAjopOogtnHZjj/Gzh56ux4sIl8cb+7WqkkYopClnkB1saOBCXzKsDPsgNsgn qFF6W0h0V6+08QAtk6cKFTSlx4R+7pRVRKlsvhaXlMjzn1fRPRxryRgo++x34fpjC9QgkT fIJoKbzOioRZWjvDowdLAqmGbIz/qBjMbCAPpStUdL0vb2aWD8HYUUp5uuuMKQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1701895443; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=tt/d27mY59C3uUO6MUg2plSSXPKh9R05K6pzapnG0gA=; b=uKMrxTVRbmTQOuVwzsvgOlKvSPYJrwjcJ2j6NmtCUTFAY0aZNpzQ6QzlKQz/zs3C1NujSf 62DSSdDBuApYu8Bg== To: Jacob Pan , LKML , X86 Kernel , iommu@lists.linux.dev, Lu Baolu , kvm@vger.kernel.org, Dave Hansen , Joerg Roedel , "H. Peter Anvin" , Borislav Petkov , Ingo Molnar Cc: Raj Ashok , "Tian, Kevin" , maz@kernel.org, peterz@infradead.org, seanjc@google.com, Robin Murphy , Jacob Pan Subject: Re: [PATCH RFC 11/13] iommu/vt-d: Add an irq_chip for posted MSIs In-Reply-To: <20231112041643.2868316-12-jacob.jun.pan@linux.intel.com> References: <20231112041643.2868316-1-jacob.jun.pan@linux.intel.com> <20231112041643.2868316-12-jacob.jun.pan@linux.intel.com> Date: Wed, 06 Dec 2023 21:44:02 +0100 Message-ID: <87wmtrt625.ffs@tglx> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain On Sat, Nov 11 2023 at 20:16, Jacob Pan wrote: > static void fill_msi_msg(struct msi_msg *msg, u32 index, u32 subhandle) > { > memset(msg, 0, sizeof(*msg)); > @@ -1361,7 +1397,7 @@ static int intel_irq_remapping_alloc(struct irq_domain *domain, > > irq_data->hwirq = (index << 16) + i; > irq_data->chip_data = ird; > - irq_data->chip = &intel_ir_chip; > + irq_data->chip = posted_msi_supported() ? &intel_ir_chip_post_msi : &intel_ir_chip; This is just wrong because you change the chip to posted for _ALL_ domains unconditionally. The only domains which want this chip are the PCI/MSI domains. And those are distinct from the domains which serve IO/APIC, HPET, no? So you can set that chip only for PCI/MSI and just let IO/APIC, HPET domains keep the original chip, which spares any modification of the IO/APIC domain.