Re: [kvm-unit-tests PATCH] x86: tscdeadline timer testing when apic is hw disabled

[Vitaly Kuznetsov <vkuznets@redhat.com>]

Wanpeng Li <kernellwp@gmail.com> writes:

> From: Wanpeng Li <wanpengli@tencent.com>
>
> This patch adds tscdeadline timer testing when apic is hw disabled.
>
> Signed-off-by: Wanpeng Li <wanpengli@tencent.com>
> ---
>  x86/apic.c | 27 +++++++++++++++++++++------
>  1 file changed, 21 insertions(+), 6 deletions(-)
>
> diff --git a/x86/apic.c b/x86/apic.c
> index a7681fe..bcf56e2 100644
> --- a/x86/apic.c
> +++ b/x86/apic.c
> @@ -30,15 +30,18 @@ static void tsc_deadline_timer_isr(isr_regs_t *regs)
>      eoi();
>  }
>  
> -static void __test_tsc_deadline_timer(void)
> +static void __test_tsc_deadline_timer(bool apic_enabled)
>  {
>      handle_irq(TSC_DEADLINE_TIMER_VECTOR, tsc_deadline_timer_isr);
>      irq_enable();
>  
>      wrmsr(MSR_IA32_TSCDEADLINE, rdmsr(MSR_IA32_TSC));
>      asm volatile ("nop");
> -    report(tdt_count == 1, "tsc deadline timer");
> -    report(rdmsr(MSR_IA32_TSCDEADLINE) == 0, "tsc deadline timer clearing");
> +    if (apic_enabled) {
> +        report(tdt_count == 1, "tsc deadline timer");
> +        report(rdmsr(MSR_IA32_TSCDEADLINE) == 0, "tsc deadline timer clearing");
> +    } else
> +        report(rdmsr(MSR_IA32_TSCDEADLINE) == 0, "tsc deadline timer is not set");

I'd suggest we also check that the timer didn't fire, e.g.

report(tdt_count == 0, "tsc deadline timer didn't fire");

as a bonus, we'd get another reason to use braces for both branches of
the 'if' (which is a good thing regardless).

>  }
>  
>  static int enable_tsc_deadline_timer(void)
> @@ -54,10 +57,10 @@ static int enable_tsc_deadline_timer(void)
>      }
>  }
>  
> -static void test_tsc_deadline_timer(void)
> +static void test_tsc_deadline_timer(bool apic_enabled)
>  {
>      if(enable_tsc_deadline_timer()) {
> -        __test_tsc_deadline_timer();
> +        __test_tsc_deadline_timer(apic_enabled);
>      } else {
>          report_skip("tsc deadline timer not detected");
>      }
> @@ -132,6 +135,17 @@ static void verify_disabled_apic_mmio(void)
>      write_cr8(cr8);
>  }
>  
> +static void verify_disabled_apic_tsc_deadline_timer(void)
> +{
> +    reset_apic();
> +    if (enable_tsc_deadline_timer()) {
> +        disable_apic();
> +        __test_tsc_deadline_timer(false);
> +    } else {
> +        report_skip("tsc deadline timer not detected");
> +    }
> +}
> +
>  static void test_apic_disable(void)
>  {
>      volatile u32 *lvr = (volatile u32 *)(APIC_DEFAULT_PHYS_BASE + APIC_LVR);
> @@ -148,6 +162,7 @@ static void test_apic_disable(void)
>      report(!this_cpu_has(X86_FEATURE_APIC),
>             "CPUID.1H:EDX.APIC[bit 9] is clear");
>      verify_disabled_apic_mmio();
> +    verify_disabled_apic_tsc_deadline_timer();
>  
>      reset_apic();
>      report((rdmsr(MSR_IA32_APICBASE) & (APIC_EN | APIC_EXTD)) == APIC_EN,
> @@ -668,7 +683,7 @@ int main(void)
>  
>      test_apic_timer_one_shot();
>      test_apic_change_mode();
> -    test_tsc_deadline_timer();
> +    test_tsc_deadline_timer(true);
>  
>      return report_summary();
>  }

-- 
Vitaly