From mboxrd@z Thu Jan 1 00:00:00 1970 From: Anthony Liguori Subject: Re: [Qemu-devel] KVM call minutes 2013-01-29 - Port I/O Date: Wed, 30 Jan 2013 07:24:57 -0600 Message-ID: <87y5fa6bx2.fsf@codemonkey.ws> References: <871ud4gfoa.fsf@elfo.elfo> <5109065B.4060803@suse.de> <20130130123156.GA406@redhat.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: QUOTED-PRINTABLE Cc: Andreas =?utf-8?Q?F=C3=A4rber?= , Juan Quintela , KVM devel mailing list , qemu-devel , Alexander Graf , =?utf-8?Q?Herv=C3=A9?= Poussineau , Gerd Hoffmann , qemu-ppc , Alon Levy , David Gibson To: "Michael S. Tsirkin" , Peter Maydell Return-path: Received: from mail-ia0-f172.google.com ([209.85.210.172]:51606 "EHLO mail-ia0-f172.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753600Ab3A3NZD convert rfc822-to-8bit (ORCPT ); Wed, 30 Jan 2013 08:25:03 -0500 Received: by mail-ia0-f172.google.com with SMTP id u8so2323747iag.31 for ; Wed, 30 Jan 2013 05:25:01 -0800 (PST) In-Reply-To: <20130130123156.GA406@redhat.com> Sender: kvm-owner@vger.kernel.org List-ID: "Michael S. Tsirkin" writes: > On Wed, Jan 30, 2013 at 11:48:14AM +0000, Peter Maydell wrote: >> On 30 January 2013 11:39, Andreas F=C3=A4rber wro= te: >> > Proposal by hpoussin was to move _list_add() code to ISADevice: >> > http://lists.gnu.org/archive/html/qemu-devel/2013-01/msg00508.html >> > >> > Concerns: >> > * PCI devices (VGA, QXL) register I/O ports as well >> > =3D> above patches add dependency on ISABus to machines >> > -> " no mac ever had one" >> > =3D> PCIDevice shouldn't use ISA API with NULL ISADevice >> > * Lack of avi: Who decides about memory API these days? >> > >> > armbru and agraf concluded that moving this into ISA is wrong. >> > >> > =3D> I will drop the remaining ioport patches from above series. >> > >> > Suggestions on how to proceed with tackling the issue are welcome. >>=20 >> How does this stuff work on real hardware? I would have >> expected that a PCI device registering the fact it has >> IO ports would have to do so via the PCI controller it >> is plugged into... > > All programming is done by the OS, devices do not register > with controller. > > Each bridge has two ways to claim an IO transaction: > - transaction is within the window programmed in the bridge > - subtractive decoding enabled and no one else claims the transaction And there can only be one endpoint that accepts subtractive decoding an= d this is usually the ISA bridge. Also note that there are some really special cases with PCI. The legac= y VGA ports are always routed to the first device with a DISPLAY class type. Likewise, with legacy IDE ports are routed to the first device with an IDE class. That's the only reason you can have these legacy devices no= t behind the ISA bridge. Regards, Anthony Liguori > > At the bus level, transaction happens on a bus and an appropriate dev= ice > will claim it. > >> My naive don't-know-much-about-portio suggestion is that this >> should work the same way as memory regions: each device >> provides portio regions, and the controller for the bus >> (ISA or PCI) exposes those to the next layer up, and >> something at board level maps it all into the right places. >>=20 >> -- PMM