public inbox for kvm@vger.kernel.org
 help / color / mirror / Atom feed
From: Manali Shukla <manali.shukla@amd.com>
To: Naveen N Rao <naveen@kernel.org>
Cc: <kvm@vger.kernel.org>, <linux-perf-users@vger.kernel.org>,
	<linux-doc@vger.kernel.org>, <seanjc@google.com>,
	<pbonzini@redhat.com>, <nikunj@amd.com>, <bp@alien8.de>,
	<peterz@infradead.org>, <mingo@redhat.com>, <mizhang@google.com>,
	<thomas.lendacky@amd.com>, <ravi.bangoria@amd.com>,
	<Sandipan.Das@amd.com>
Subject: Re: [PATCH v2 02/12] KVM: x86: Refactor APIC register mask handling to support extended APIC registers
Date: Mon, 13 Oct 2025 11:23:50 +0530	[thread overview]
Message-ID: <8aa1c06d-bfb5-49ef-b452-3445481d8b8e@amd.com> (raw)
In-Reply-To: <koech6fbxpzzao3232pf4ozloanas4irecti2n3win2ow7aikj@3r72i5qyaxd4>

Hi Naveen,

On 10/6/2025 9:42 PM, Naveen N Rao wrote:
> On Mon, Sep 01, 2025 at 10:51:18AM +0530, Manali Shukla wrote:
>> Modify the APIC register mask infrastructure to support both standard
>> APIC registers (0x0-0x3f0) and extended APIC registers (0x400-0x530).
>>
>> This refactoring:
>> - Replaces the single u64 bitmask with a u64[2] array to accommodate
>>   the extended register range(128 bitmask)
>> - Updates the APIC_REG_MASK macro to handle both standard and extended
>>   register spaces
>> - Adapts kvm_lapic_readable_reg_mask() to use the new approach
>> - Adds APIC_REG_TEST macro to check register validity for standard
>>   APIC registers and Exended APIC registers
>> - Updates all callers to use the new interface
>>
>> This is purely an infrastructure change to support the upcoming
>> extended APIC register emulation.
>>
>> Suggested-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
>> Signed-off-by: Manali Shukla <manali.shukla@amd.com>
>> ---
>>  arch/x86/kvm/lapic.c   | 99 ++++++++++++++++++++++++++----------------
>>  arch/x86/kvm/lapic.h   |  2 +-
>>  arch/x86/kvm/vmx/vmx.c | 10 +++--
>>  3 files changed, 70 insertions(+), 41 deletions(-)
>>
>> diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
>> index e19545b8cc98..f92e3f53ee75 100644
>> --- a/arch/x86/kvm/lapic.c
>> +++ b/arch/x86/kvm/lapic.c
>> @@ -1587,53 +1587,77 @@ static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
>>  	return container_of(dev, struct kvm_lapic, dev);
>>  }
>>  
>> -#define APIC_REG_MASK(reg)	(1ull << ((reg) >> 4))
>> -#define APIC_REGS_MASK(first, count) \
>> -	(APIC_REG_MASK(first) * ((1ull << (count)) - 1))
>> -
>> -u64 kvm_lapic_readable_reg_mask(struct kvm_lapic *apic)
>> -{
>> -	/* Leave bits '0' for reserved and write-only registers. */
>> -	u64 valid_reg_mask =
>> -		APIC_REG_MASK(APIC_ID) |
>> -		APIC_REG_MASK(APIC_LVR) |
>> -		APIC_REG_MASK(APIC_TASKPRI) |
>> -		APIC_REG_MASK(APIC_PROCPRI) |
>> -		APIC_REG_MASK(APIC_LDR) |
>> -		APIC_REG_MASK(APIC_SPIV) |
>> -		APIC_REGS_MASK(APIC_ISR, APIC_ISR_NR) |
>> -		APIC_REGS_MASK(APIC_TMR, APIC_ISR_NR) |
>> -		APIC_REGS_MASK(APIC_IRR, APIC_ISR_NR) |
>> -		APIC_REG_MASK(APIC_ESR) |
>> -		APIC_REG_MASK(APIC_ICR) |
>> -		APIC_REG_MASK(APIC_LVTT) |
>> -		APIC_REG_MASK(APIC_LVTTHMR) |
>> -		APIC_REG_MASK(APIC_LVTPC) |
>> -		APIC_REG_MASK(APIC_LVT0) |
>> -		APIC_REG_MASK(APIC_LVT1) |
>> -		APIC_REG_MASK(APIC_LVTERR) |
>> -		APIC_REG_MASK(APIC_TMICT) |
>> -		APIC_REG_MASK(APIC_TMCCT) |
>> -		APIC_REG_MASK(APIC_TDCR);
>> +/*
>> + * Helper macros for APIC register bitmask handling
>> + * 2 element array is being used to represent 128-bit mask, where:
>> + * - mask[0] tracks standard APIC registers (0x0-0x3f0)
>> + * - mask[1] tracks extended APIC registers (0x400-0x530)
>> + */
>> +
>> +#define APIC_REG_INDEX(reg)	(((reg) < 0x400) ? 0 : 1)
>> +#define APIC_REG_BIT(reg)	(((reg) < 0x400) ? ((reg) >> 4) : (((reg) - 0x400) >> 4))
>> +
>> +/* Set a bit in the mask for a single APIC register. */
>> +#define APIC_REG_MASK(reg, mask) do { \
>> +	(mask)[APIC_REG_INDEX(reg)] |= (1ULL << APIC_REG_BIT(reg)); \
>> +} while (0)
>> +
>> +/* Set bits in the mask for a range of consecutive APIC registers. */
>> +#define APIC_REGS_MASK(first, count, mask) do { \
>> +	(mask)[APIC_REG_INDEX(first)] |= ((1ULL << (count)) - 1) << APIC_REG_BIT(first); \
>> +} while (0)
>> +
>> +/* Macro to check whether the an APIC register bit is set in the mask. */
>> +#define APIC_REG_TEST(reg, mask) \
>> +	((mask)[APIC_REG_INDEX(reg)] & (1ULL << APIC_REG_BIT(reg)))
>> +
>> +#define APIC_LAST_REG_OFFSET		0x3f0
>> +#define APIC_EXT_LAST_REG_OFFSET	0x530
>> +
>> +void kvm_lapic_readable_reg_mask(struct kvm_lapic *apic, u64 mask[2])
>> +{
>> +	mask[0] = 0;
>> +	mask[1] = 0;
> 
> Would it be simpler to use a bitmap for the mask?
> 
> 
> - Naveen
> 

Thanks for the suggestion. I'll revisit this code and explore using
the bitmap APIs from lib/bitmap.c and include/linux/bitmap.h. I'll
include any improvements in v3.

-Manali

  reply	other threads:[~2025-10-13  5:54 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-09-01  5:16 [PATCH v2 00/12] Implement support for IBS virtualization Manali Shukla
2025-09-01  5:19 ` [PATCH v2 01/12] perf/amd/ibs: Fix race condition in IBS Manali Shukla
2025-09-01  5:21 ` [PATCH v2 02/12] KVM: x86: Refactor APIC register mask handling to support extended APIC registers Manali Shukla
2025-10-06 16:12   ` Naveen N Rao
2025-10-13  5:53     ` Manali Shukla [this message]
2025-09-01  5:21 ` [PATCH v2 03/12] KVM: Add KVM_GET_EXT_LAPIC and KVM_SET_EXT_LAPIC for extapic Manali Shukla
2025-12-16 14:21   ` Naveen N Rao
2026-01-14 21:59     ` Sean Christopherson
2026-01-22 14:53       ` Manali Shukla
2025-09-01  5:22 ` [PATCH v2 04/12] x86/cpufeatures: Add CPUID feature bit for Extended LVT Manali Shukla
2025-09-08 13:39   ` Naveen N Rao
2025-09-17 15:34     ` Manali Shukla
2025-10-08  6:58       ` Naveen N Rao
2025-10-13  5:36         ` Manali Shukla
2025-09-01  5:22 ` [PATCH v2 05/12] KVM: x86: Add emulation support for Extented LVT registers Manali Shukla
2025-09-08 13:41   ` Naveen N Rao
2025-09-17 12:57     ` Manali Shukla
2025-10-08  7:00       ` Naveen N Rao
2025-10-13  5:38         ` Manali Shukla
2025-09-01  5:23 ` [PATCH v2 06/12] x86/cpufeatures: Add CPUID feature bit for VIBS in SVM/SEV guests Manali Shukla
2025-09-10 13:01   ` Nikunj A Dadhania
2025-09-17 15:40     ` Manali Shukla
2025-09-01  5:23 ` [PATCH v2 07/12] KVM: x86/cpuid: Add a KVM-only leaf for IBS capabilities Manali Shukla
2025-09-01  5:24 ` [PATCH v2 08/12] KVM: x86: Extend CPUID range to include new leaf Manali Shukla
2025-09-01  5:24 ` [PATCH v2 09/12] KVM: SVM: Extend VMCB area for virtualized IBS registers Manali Shukla
2025-09-01  5:25 ` [PATCH v2 10/12] KVM: SVM: Add support for IBS Virtualization Manali Shukla
2025-10-08  7:30   ` Naveen N Rao
2025-09-01  5:26 ` [PATCH v2 11/12] perf/x86/amd: Enable VPMU passthrough capability for IBS PMU Manali Shukla
2025-09-01  5:26 ` [PATCH v2 12/12] perf/x86/amd: Remove exclude_guest check from perf_ibs_init() Manali Shukla

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=8aa1c06d-bfb5-49ef-b452-3445481d8b8e@amd.com \
    --to=manali.shukla@amd.com \
    --cc=Sandipan.Das@amd.com \
    --cc=bp@alien8.de \
    --cc=kvm@vger.kernel.org \
    --cc=linux-doc@vger.kernel.org \
    --cc=linux-perf-users@vger.kernel.org \
    --cc=mingo@redhat.com \
    --cc=mizhang@google.com \
    --cc=naveen@kernel.org \
    --cc=nikunj@amd.com \
    --cc=pbonzini@redhat.com \
    --cc=peterz@infradead.org \
    --cc=ravi.bangoria@amd.com \
    --cc=seanjc@google.com \
    --cc=thomas.lendacky@amd.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox