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Wed, 06 May 2020 10:39:59 +0100 MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII; format=flowed Content-Transfer-Encoding: 7bit Date: Wed, 06 May 2020 10:39:59 +0100 From: Marc Zyngier To: Andrew Scull Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, Will Deacon , Andre Przywara , Dave Martin , George Cherian , "Zengtao (B)" , Catalin Marinas Subject: Re: [PATCH 05/26] arm64: Document SW reserved PTE/PMD bits in Stage-2 descriptors In-Reply-To: <20200505155916.GB237572@google.com> References: <20200422120050.3693593-1-maz@kernel.org> <20200422120050.3693593-6-maz@kernel.org> <20200505155916.GB237572@google.com> User-Agent: Roundcube Webmail/1.4.3 Message-ID: <8b399c95ca1393e63cc1077ede8a45f6@kernel.org> X-Sender: maz@kernel.org X-SA-Exim-Connect-IP: 51.254.78.96 X-SA-Exim-Rcpt-To: ascull@google.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, will@kernel.org, andre.przywara@arm.com, Dave.Martin@arm.com, gcherian@marvell.com, prime.zeng@hisilicon.com, catalin.marinas@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Hi Andrew, On 2020-05-05 16:59, Andrew Scull wrote: > On Wed, Apr 22, 2020 at 01:00:29PM +0100, Marc Zyngier wrote: >> Advertise bits [58:55] as reserved for SW in the S2 descriptors. >> >> Signed-off-by: Marc Zyngier >> --- >> arch/arm64/include/asm/pgtable-hwdef.h | 2 ++ >> 1 file changed, 2 insertions(+) >> >> diff --git a/arch/arm64/include/asm/pgtable-hwdef.h >> b/arch/arm64/include/asm/pgtable-hwdef.h >> index 6bf5e650da788..7eab0d23cdb52 100644 >> --- a/arch/arm64/include/asm/pgtable-hwdef.h >> +++ b/arch/arm64/include/asm/pgtable-hwdef.h >> @@ -177,10 +177,12 @@ >> #define PTE_S2_RDONLY (_AT(pteval_t, 1) << 6) /* HAP[2:1] */ >> #define PTE_S2_RDWR (_AT(pteval_t, 3) << 6) /* HAP[2:1] */ >> #define PTE_S2_XN (_AT(pteval_t, 2) << 53) /* XN[1:0] */ >> +#define PTE_S2_SW_RESVD (_AT(pteval_t, 15) << 55) /* Reserved for SW >> */ >> >> #define PMD_S2_RDONLY (_AT(pmdval_t, 1) << 6) /* HAP[2:1] */ >> #define PMD_S2_RDWR (_AT(pmdval_t, 3) << 6) /* HAP[2:1] */ >> #define PMD_S2_XN (_AT(pmdval_t, 2) << 53) /* XN[1:0] */ >> +#define PMD_S2_SW_RESVD (_AT(pmdval_t, 15) << 55) /* Reserved for SW >> */ >> >> #define PUD_S2_RDONLY (_AT(pudval_t, 1) << 6) /* HAP[2:1] */ >> #define PUD_S2_RDWR (_AT(pudval_t, 3) << 6) /* HAP[2:1] */ >> -- >> 2.26.1 >> >> _______________________________________________ >> kvmarm mailing list >> kvmarm@lists.cs.columbia.edu >> https://lists.cs.columbia.edu/mailman/listinfo/kvmarm > > This is consistent with "Attribute fields in stage 1 VMSAv8-64 Block > and > Page descriptors" Do you mean "stage 2" instead? The reserved bits are the same, but I want to be sure we have looked at the same thing (ARM DDI 0487F.a, D5-2603). > Reviewed-by: Andrew Scull Thanks, M. -- Jazz is not dead. It just smells funny...