From: Marc Zyngier <maz@kernel.org>
To: Ard Biesheuvel <ardb@kernel.org>
Cc: Linux ARM <linux-arm-kernel@lists.infradead.org>,
kvmarm <kvmarm@lists.cs.columbia.edu>,
kvm@vger.kernel.org, James Morse <james.morse@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Alexandru Elisei <alexandru.elisei@arm.com>,
Android Kernel Team <kernel-team@android.com>
Subject: Re: [PATCH] KVM: arm64: vgic-v3: Restrict SEIS workaround to known broken systems
Date: Sat, 22 Jan 2022 11:32:45 +0000 [thread overview]
Message-ID: <8d8b93e7251b0373d897a2f9222b0520@kernel.org> (raw)
In-Reply-To: <CAMj1kXEmNpTGtZU=ZkOTpYpG7bdaubUx3-Zzpf-D1unjk43AYQ@mail.gmail.com>
On 2022-01-22 11:14, Ard Biesheuvel wrote:
> On Sat, 22 Jan 2022 at 11:39, Marc Zyngier <maz@kernel.org> wrote:
>>
>> Contrary to what df652bcf1136 ("KVM: arm64: vgic-v3: Work around GICv3
>> locally generated SErrors") was asserting, there is at least one other
>> system out there (Cavium ThunderX2) implementing SEIS, and not in
>> an obviously broken way.
>>
>> So instead of imposing the M1 workaround on an innocent bystander,
>> let's limit it to the two known broken Apple implementations.
>>
>> Fixes: df652bcf1136 ("KVM: arm64: vgic-v3: Work around GICv3 locally
>> generated SErrors")
>> Reported-by: Ard Biesheuvel <ardb@kernel.org>
>> Signed-off-by: Marc Zyngier <maz@kernel.org>
>
> Thanks for the fix.
>
> Tested-by: Ard Biesheuvel <ardb@kernel.org>
> Acked-by: Ard Biesheuvel <ardb@kernel.org>
Thanks for that.
>
> One nit below.
>
>> ---
>> arch/arm64/kvm/hyp/vgic-v3-sr.c | 3 +++
>> arch/arm64/kvm/vgic/vgic-v3.c | 17 +++++++++++++++--
>> 2 files changed, 18 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm64/kvm/hyp/vgic-v3-sr.c
>> b/arch/arm64/kvm/hyp/vgic-v3-sr.c
>> index 20db2f281cf2..4fb419f7b8b6 100644
>> --- a/arch/arm64/kvm/hyp/vgic-v3-sr.c
>> +++ b/arch/arm64/kvm/hyp/vgic-v3-sr.c
>> @@ -983,6 +983,9 @@ static void __vgic_v3_read_ctlr(struct kvm_vcpu
>> *vcpu, u32 vmcr, int rt)
>> val = ((vtr >> 29) & 7) << ICC_CTLR_EL1_PRI_BITS_SHIFT;
>> /* IDbits */
>> val |= ((vtr >> 23) & 7) << ICC_CTLR_EL1_ID_BITS_SHIFT;
>> + /* SEIS */
>> + if (kvm_vgic_global_state.ich_vtr_el2 & ICH_VTR_SEIS_MASK)
>> + val |= BIT(ICC_CTLR_EL1_SEIS_SHIFT);
>> /* A3V */
>> val |= ((vtr >> 21) & 1) << ICC_CTLR_EL1_A3V_SHIFT;
>> /* EOImode */
>> diff --git a/arch/arm64/kvm/vgic/vgic-v3.c
>> b/arch/arm64/kvm/vgic/vgic-v3.c
>> index 78cf674c1230..d34a795f730c 100644
>> --- a/arch/arm64/kvm/vgic/vgic-v3.c
>> +++ b/arch/arm64/kvm/vgic/vgic-v3.c
>> @@ -609,6 +609,18 @@ static int __init early_gicv4_enable(char *buf)
>> }
>> early_param("kvm-arm.vgic_v4_enable", early_gicv4_enable);
>>
>> +static struct midr_range broken_seis[] = {
>
> Can this be const?
Absolutely. I'll fold that in.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
prev parent reply other threads:[~2022-01-22 11:32 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-22 10:39 [PATCH] KVM: arm64: vgic-v3: Restrict SEIS workaround to known broken systems Marc Zyngier
2022-01-22 11:14 ` Ard Biesheuvel
2022-01-22 11:32 ` Marc Zyngier [this message]
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