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X-CSE-ConnectionGUID: QEFsWR3jSuOGzz63pm7PrA== X-CSE-MsgGUID: 9B+1y2O4T7WUHv/ic5z9Yw== X-IronPort-AV: E=McAfee;i="6800,10657,11459"; a="51771260" X-IronPort-AV: E=Sophos;i="6.16,224,1744095600"; d="scan'208";a="51771260" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jun 2025 23:21:10 -0700 X-CSE-ConnectionGUID: EvT91XccR8qL2MtfgcrCnQ== X-CSE-MsgGUID: DP1cOW1pSV+4XWpQL/wpYQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,224,1744095600"; d="scan'208";a="146656509" Received: from dapengmi-mobl1.ccr.corp.intel.com (HELO [10.124.245.144]) ([10.124.245.144]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jun 2025 23:21:07 -0700 Message-ID: <92b737d4-4584-4e8c-89dc-e2a5308449ec@linux.intel.com> Date: Tue, 10 Jun 2025 14:21:04 +0800 Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [kvm-unit-tests PATCH 06/16] x86: Add and use X86_PROPERTY_INTEL_PT_NR_RANGES To: Sean Christopherson , Andrew Jones , Janosch Frank , Claudio Imbrenda , =?UTF-8?Q?Nico_B=C3=B6hr?= , Paolo Bonzini Cc: kvm-riscv@lists.infradead.org, linux-s390@vger.kernel.org, kvm@vger.kernel.org References: <20250529221929.3807680-1-seanjc@google.com> <20250529221929.3807680-7-seanjc@google.com> Content-Language: en-US From: "Mi, Dapeng" In-Reply-To: <20250529221929.3807680-7-seanjc@google.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 5/30/2025 6:19 AM, Sean Christopherson wrote: > Add a definition for X86_PROPERTY_INTEL_PT_NR_RANGES, and use it instead > of open coding equivalent logic in the LA57 testcase that verifies the > canonical address behavior of PT MSRs. > > No functional change intended. > > Signed-off-by: Sean Christopherson > --- > lib/x86/processor.h | 3 +++ > x86/la57.c | 2 +- > 2 files changed, 4 insertions(+), 1 deletion(-) > > diff --git a/lib/x86/processor.h b/lib/x86/processor.h > index cbfd2ee1..3b02a966 100644 > --- a/lib/x86/processor.h > +++ b/lib/x86/processor.h > @@ -370,6 +370,9 @@ struct x86_cpu_property { > > #define X86_PROPERTY_XSTATE_TILE_SIZE X86_CPU_PROPERTY(0xd, 18, EAX, 0, 31) > #define X86_PROPERTY_XSTATE_TILE_OFFSET X86_CPU_PROPERTY(0xd, 18, EBX, 0, 31) > + > +#define X86_PROPERTY_INTEL_PT_NR_RANGES X86_CPU_PROPERTY(0x14, 1, EAX, 0, 2) > + > #define X86_PROPERTY_AMX_MAX_PALETTE_TABLES X86_CPU_PROPERTY(0x1d, 0, EAX, 0, 31) > #define X86_PROPERTY_AMX_TOTAL_TILE_BYTES X86_CPU_PROPERTY(0x1d, 1, EAX, 0, 15) > #define X86_PROPERTY_AMX_BYTES_PER_TILE X86_CPU_PROPERTY(0x1d, 1, EAX, 16, 31) > diff --git a/x86/la57.c b/x86/la57.c > index 41764110..1161a5bf 100644 > --- a/x86/la57.c > +++ b/x86/la57.c > @@ -288,7 +288,7 @@ static void __test_canonical_checks(bool force_emulation) > > /* PT filter ranges */ > if (this_cpu_has(X86_FEATURE_INTEL_PT)) { > - int n_ranges = cpuid_indexed(0x14, 0x1).a & 0x7; > + int n_ranges = this_cpu_property(X86_PROPERTY_INTEL_PT_NR_RANGES); > int i; > > for (i = 0 ; i < n_ranges ; i++) { Reviewed-by: Dapeng Mi