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([2001:b07:6468:f312:1032:7ea1:7f8f:1e5]) by smtp.gmail.com with ESMTPSA id w125sm7359506wmg.32.2019.10.09.14.40.53 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 09 Oct 2019 14:40:54 -0700 (PDT) Subject: Re: [Patch 3/6] kvm: svm: Add support for XSAVES on AMD To: Jim Mattson Cc: Aaron Lewis , Babu Moger , Yang Weijiang , Sebastian Andrzej Siewior , kvm list , Luwei Kang References: <20191009004142.225377-1-aaronlewis@google.com> <20191009004142.225377-3-aaronlewis@google.com> <56cf7ca1-d488-fc6e-1c20-b477dd855d84@redhat.com> From: Paolo Bonzini Openpgp: preference=signencrypt Message-ID: <9335c3c7-e2dd-cb2d-454a-c41143c94b63@redhat.com> Date: Wed, 9 Oct 2019 23:40:52 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-MC-Unique: s1bpaoAaMfe3LaJzE1Vsdg-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On 09/10/19 23:29, Jim Mattson wrote: > On Wed, Oct 9, 2019 at 12:02 AM Paolo Bonzini wrote= : >> >> On 09/10/19 02:41, Aaron Lewis wrote: >>> - /* >>> - * The only supported bit as of Skylake is bit 8, but >>> - * it is not supported on KVM. >>> - */ >>> - if (data !=3D 0) >>> - return 1; >> >> This comment is actually not true anymore; Intel supports PT (bit 8) on >> Cascade Lake, so it could be changed to something like >> >> /* >> * We do support PT (bit 8) if kvm_x86_ops->pt_supported(), but >> * guests will have to configure it using WRMSR rather than >> * XSAVES. >> */ >> >> Paolo >=20 > Isn't it necessary for the host to set IA32_XSS to a superset of the > guest IA32_XSS for proper host-level context-switching? Yes, this is why we cannot allow the guest to set bit 8. But the comment is obsolete: 1) of course Skylake is not the newest model 2) processor tracing was not supported at all when the comment was written; but on CascadeLake, guest PT is now supported---just not the processor tracing XSAVES component. Paolo > arch/x86/kernel/fpu/xstate.c has this comment: >=20 > * Note that we do not currently set any bits on IA32_XSS so > * 'XCR0 | IA32_XSS =3D=3D XCR0' for now. >=20