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From: Yu Zhang <yu.c.zhang@linux.intel.com>
To: Paolo Bonzini <pbonzini@redhat.com>, kvm@vger.kernel.org
Cc: linux-kernel@vger.kernel.org, rkrcmar@redhat.com,
	tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com,
	xiaoguangrong@tencent.com, joro@8bytes.org
Subject: Re: [PATCH v1 1/4] KVM: MMU: check guest CR3 reserved bits based on its physical address width.
Date: Mon, 14 Aug 2017 19:39:01 +0800	[thread overview]
Message-ID: <93d301f3-7fdc-866c-a140-4afe0c0a8dab@linux.intel.com> (raw)
In-Reply-To: <c128d21e-861c-1d3b-625b-c87ce80b22e6@redhat.com>



On 8/14/2017 3:36 PM, Paolo Bonzini wrote:
> On 12/08/2017 15:35, Yu Zhang wrote:
>> +			ctxt->ops->get_cpuid(ctxt, &eax, NULL, NULL, NULL);
>> +			maxphyaddr = eax * 0xff;
> This is "&", not "*".  You can also use rsvd_bits here.

Oops. Sorry for the typo. :-)

>> +			rsvd = (~((1UL << maxphyaddr) - 1)) &
>> +				~CR3_PCID_INVD;
>> +		}
>>   
>>   		if (new_val & rsvd)
>>   			return emulate_gp(ctxt, 0);
>> diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
>> index e40a779..d9100c4 100644
>> --- a/arch/x86/kvm/x86.c
>> +++ b/arch/x86/kvm/x86.c
>> @@ -813,10 +813,10 @@ int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
>>   		return 0;
>>   	}
>>   
>> -	if (is_long_mode(vcpu)) {
>> -		if (cr3 & CR3_L_MODE_RESERVED_BITS)
>> -			return 1;
>> -	} else if (is_pae(vcpu) && is_paging(vcpu) &&
>> +	if (is_long_mode(vcpu) &&
>> +	    (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
>> +		return 1;
> 62 is a little better, since 63 is the PCID invalidate bit.

Got it. Both kvm_set_cr3() and check_cr_write() should use 
rsvd_bits(maxphyaddr, 62) .

Thanks
Yu

> Paolo
>
>> +	else if (is_pae(vcpu) && is_paging(vcpu) &&
>>   		   !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
>>   		return 1;
>>   
>

  reply	other threads:[~2017-08-14 11:39 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-08-12 13:35 [PATCH v1 0/4] KVM: MMU: 5 level EPT/shadow support Yu Zhang
2017-08-12 13:35 ` [PATCH v1 1/4] KVM: MMU: check guest CR3 reserved bits based on its physical address width Yu Zhang
2017-08-14  7:36   ` Paolo Bonzini
2017-08-14 11:39     ` Yu Zhang [this message]
2017-08-14 16:13   ` Jim Mattson
2017-08-14 16:40     ` Paolo Bonzini
2017-08-15  7:50       ` Yu Zhang
2017-08-12 13:35 ` [PATCH v1 2/4] KVM: MMU: Rename PT64_ROOT_LEVEL to PT64_ROOT_4LEVEL Yu Zhang
2017-08-12 13:35 ` [PATCH v1 3/4] KVM: MMU: Add 5 level EPT & Shadow page table support Yu Zhang
2017-08-14  7:31   ` Paolo Bonzini
2017-08-14 11:37     ` Yu Zhang
2017-08-14 14:13       ` Paolo Bonzini
2017-08-14 14:32         ` Yu Zhang
2017-08-14 15:02           ` Paolo Bonzini
2017-08-14 14:55             ` Yu Zhang
2017-08-12 13:35 ` [PATCH v1 4/4] KVM: MMU: Expose the LA57 feature to VM Yu Zhang
2017-08-17 11:57   ` Paolo Bonzini
2017-08-17 11:53     ` Yu Zhang
2017-08-17 14:29       ` Paolo Bonzini
2017-08-18  8:28         ` Yu Zhang
2017-08-18 12:50           ` Paolo Bonzini
2017-08-21  7:27             ` Yu Zhang
2017-08-21 10:12               ` Paolo Bonzini
2017-08-21 12:11                 ` Yu Zhang
2017-08-14  7:32 ` [PATCH v1 0/4] KVM: MMU: 5 level EPT/shadow support Paolo Bonzini

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