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X-CSE-ConnectionGUID: TayZ3JZgSpiX8jmdjBn6jg== X-CSE-MsgGUID: 5AHybgb9Qu2JH5RAIdN2DA== X-IronPort-AV: E=McAfee;i="6800,10657,11900"; a="106818187" X-IronPort-AV: E=Sophos;i="6.25,271,1779174000"; d="scan'208";a="106818187" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Sep 2026 19:53:09 -0700 X-CSE-ConnectionGUID: entTxNr5TDCEv2YWLqXTjw== X-CSE-MsgGUID: DrUr9IbpQpKwqWC2KM5Atg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,271,1779174000"; d="scan'208";a="296459852" Received: from unknown (HELO [10.238.208.122]) ([10.238.208.122]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Sep 2026 19:53:06 -0700 Message-ID: <94b3473c-7e44-4f6f-8721-b43ff4e2c423@intel.com> Date: Thu, 10 Sep 2026 10:53:03 +0800 Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 1/4] KVM: TDX: Track configurable CPUID bits allowed by KVM To: "Edgecombe, Rick P" , "seanjc@google.com" Cc: "Gao, Chao" , "dave.hansen@linux.intel.com" , "kas@kernel.org" , "binbin.wu@linux.intel.com" , "linux-kernel@vger.kernel.org" , "kvm@vger.kernel.org" , "pbonzini@redhat.com" , "nik.borisov@suse.com" , "andrew.cooper3@citrix.com" References: <20260827031837.2863609-1-binbin.wu@linux.intel.com> <20260827031837.2863609-2-binbin.wu@linux.intel.com> <55488b92-66a8-45e5-ad0f-8fed63ce1187@intel.com> <6b565572-b316-4e86-906d-f150c896fe21@intel.com> <84891108-55be-48c1-9993-c730a5334d5b@linux.intel.com> <9abeed40-bcdc-48d9-8cbb-cb87154bb9f6@intel.com> Content-Language: en-US From: Xiaoyao Li In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 9/10/2026 7:18 AM, Edgecombe, Rick P wrote: > On Wed, 2026-09-09 at 15:29 -0700, Sean Christopherson wrote: >>   Yeah, *ideally* we'd magically enable everything everywhere all at once.  In >> reality, different VM types are going to support features at different times.  >> More importantly, as Xiaoyao points out below in #1, unless we enable >> everyting in a single patch, which is probably a terrible idea in most cases, >> we'll still end up with staged/progressive enabling, i.e. we still need to >> have patches that selectively enable and advertise a feature only for the VM >> types that actually support the feature. >> >> This is all quite similar to Intel and AMD feature enabling being done at >> different times.  The biggest difference is that Intel and AMD are mutually >> exclusive and so KVM_GET_SUPPORTED_CPUID always reports the correct >> information, but TDX already provides KVM_TDX_CAPABILITIES, so AFAICT we still >> get accurate reporting for TDX, just in a slightly different way. > I think this actually surfaces another problem with TD-first enabling. > KVM_TDX_CAPABILITIES only returns the directly configurable bits. Then recall, > KVM_TDX_GET_CPUID returns the actual TDX module's view of CPUID bits to > userspace. Then userspace calls KVM_SET_CPUID to actually put them on KVM's vcpu > so they can match between Qemu, KVM and TDX > > So if a bit is enabled for KVM_TDX_CAPABILITIES, but not yet in > KVM_GET_SUPPORTED_CPUID. How should userspace interpret KVM_GET_SUPPORTED_CPUID? > It can ignore it for TDX, but that is how it can find the PV bits today.> > If we have a TD first feature, it could be a documentation update on how to > interpret it. Or we could stuff the PV bits somewhere else for TDX and say to > ignore KVM_GET_SUPPORTED_CPUID for TDX. I think we don't need to solve it before > we begin filtering like this series has. The PV bits reported in KVM_GET_SUPPORTED_CPUID are the bits supported for non-TDX VMs. Only some of them are actually supported for TDX. I would suggest reporting TDX supported PV CPUIDs in KVM_TDX_CAPABILITIES as well.