From: "Huang, Kai" <kai.huang@intel.com>
To: "Luck, Tony" <tony.luck@intel.com>,
"pbonzini@redhat.com" <pbonzini@redhat.com>,
"Hunter, Adrian" <adrian.hunter@intel.com>,
"seanjc@google.com" <seanjc@google.com>
Cc: "kvm@vger.kernel.org" <kvm@vger.kernel.org>,
"Li, Xiaoyao" <xiaoyao.li@intel.com>,
"Zhao, Yan Y" <yan.y.zhao@intel.com>,
"dave.hansen@linux.intel.com" <dave.hansen@linux.intel.com>,
"kirill.shutemov@linux.intel.com"
<kirill.shutemov@linux.intel.com>,
"binbin.wu@linux.intel.com" <binbin.wu@linux.intel.com>,
"Chatre, Reinette" <reinette.chatre@intel.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"mingo@redhat.com" <mingo@redhat.com>,
"Yamahata, Isaku" <isaku.yamahata@intel.com>,
"tony.lindgren@linux.intel.com" <tony.lindgren@linux.intel.com>,
"tglx@linutronix.de" <tglx@linutronix.de>,
"linux-edac@vger.kernel.org" <linux-edac@vger.kernel.org>,
"hpa@zytor.com" <hpa@zytor.com>,
"Annapurve, Vishal" <vannapurve@google.com>,
"Edgecombe, Rick P" <rick.p.edgecombe@intel.com>,
"bp@alien8.de" <bp@alien8.de>, "Gao, Chao" <chao.gao@intel.com>,
"x86@kernel.org" <x86@kernel.org>
Subject: Re: [PATCH 1/2] x86/mce: Fix missing address mask in recovery for errors in TDX/SEAM non-root mode
Date: Wed, 18 Jun 2025 23:57:55 +0000 [thread overview]
Message-ID: <96d035a19e04e2711d67716b9548a40793d549b2.camel@intel.com> (raw)
In-Reply-To: <SJ1PR11MB6083E80CEE14BA99F7A0E237FC72A@SJ1PR11MB6083.namprd11.prod.outlook.com>
On Wed, 2025-06-18 at 23:46 +0000, Luck, Tony wrote:
> > It's sort of hinted at in the SDM Vol 3B Figure 17-7. IA32_MCi_ADDR MSR
> > with the footnote in the diagram:
> >
> > "Useful bits in this field depend on the address methodology in use when the
> > the register state is saved."
> >
> > Maybe there is something more explicit in documentation for memory encryption?
>
>
> Section 5.1 in
> https://software.intel.com/sites/default/files/managed/a5/16/Multi-Key-Total-Memory-Encryption-Spec.pdf
>
> shows how the upper bits of the physical address are used for the :KeyID"
>
> -Tony
Yeah. So I guess it's somehow implied the KeyID bits, which are "useful
bits", are also recorded in IA32_MCi_ADDR.
next prev parent reply other threads:[~2025-06-18 23:58 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-18 12:08 [PATCH 0/2] Fixes for recovery for machine check in TDX/SEAM non-root mode Adrian Hunter
2025-06-18 12:08 ` [PATCH 1/2] x86/mce: Fix missing address mask in recovery for errors " Adrian Hunter
2025-06-18 12:36 ` Xiaoyao Li
2025-06-18 14:55 ` Dave Hansen
2025-06-19 11:57 ` Adrian Hunter
2025-06-27 15:23 ` Adrian Hunter
2025-06-27 15:25 ` Dave Hansen
2025-06-27 16:24 ` Luck, Tony
2025-06-27 16:33 ` Dave Hansen
2025-07-30 10:54 ` Adrian Hunter
2025-07-30 11:57 ` Huang, Kai
2025-07-30 14:20 ` Vishal Annapurve
2025-06-27 16:28 ` Luck, Tony
2025-06-18 23:20 ` Huang, Kai
2025-06-18 23:39 ` Luck, Tony
2025-06-18 23:46 ` Luck, Tony
2025-06-18 23:57 ` Huang, Kai [this message]
2025-06-18 23:53 ` Huang, Kai
2025-06-18 12:08 ` [PATCH 2/2] KVM: TDX: Do not clear poisoned pages Adrian Hunter
2025-06-18 12:39 ` Xiaoyao Li
2025-06-18 14:58 ` Dave Hansen
2025-06-25 14:33 ` Vishal Annapurve
2025-06-25 16:25 ` Adrian Hunter
2025-06-25 16:31 ` Dave Hansen
2025-06-25 16:42 ` Adrian Hunter
2025-06-25 16:57 ` Dave Hansen
2025-06-25 16:42 ` Edgecombe, Rick P
2025-06-25 22:32 ` Huang, Kai
2025-06-25 22:38 ` Dave Hansen
2025-06-26 1:19 ` Huang, Kai
2025-06-26 15:31 ` Luck, Tony
2025-06-26 22:20 ` Huang, Kai
2025-06-26 22:33 ` Dave Hansen
2025-06-27 0:56 ` Huang, Kai
2025-06-18 23:09 ` Huang, Kai
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