From: Nadav Amit <nadav.amit@gmail.com>
To: John Andersen <john.s.andersen@intel.com>
Cc: corbet@lwn.net, Paolo Bonzini <pbonzini@redhat.com>,
Thomas Gleixner <tglx@linutronix.de>, mingo <mingo@redhat.com>,
bp <bp@alien8.de>,
hpa@zytor.com, shuah@kernel.org, sean.j.christopherson@intel.com,
rick.p.edgecombe@intel.com, kvm@vger.kernel.org,
kernel-hardening@lists.openwall.com
Subject: Re: [kvm-unit-tests PATCH] x86: Add control register pinning tests
Date: Wed, 17 Jun 2020 15:52:59 -0700 [thread overview]
Message-ID: <ACCCF382-0077-4B08-8CF1-73C561F930CD@gmail.com> (raw)
In-Reply-To: <20200617224606.27954-1-john.s.andersen@intel.com>
> On Jun 17, 2020, at 3:46 PM, John Andersen <john.s.andersen@intel.com> wrote:
>
> Paravirutalized control register pinning adds MSRs guests can use to
> discover which bits in CR0/4 they may pin, and MSRs for activating
> pinning for any of those bits.
>
[ sni[
> +static void vmx_cr_pin_test_guest(void)
> +{
> + unsigned long i, cr0, cr4;
> +
> + /* Step 1. Skip feature detection to skip handling VMX_CPUID */
> + /* nop */
I do not quite get this comment. Why do you skip checking whether the
feature is enabled? What happens if KVM/bare-metal/other-hypervisor that
runs this test does not support this feature?
next prev parent reply other threads:[~2020-06-17 22:53 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-17 22:46 [kvm-unit-tests PATCH] x86: Add control register pinning tests John Andersen
2020-06-17 22:52 ` Nadav Amit [this message]
2020-06-18 3:18 ` Nadav Amit
2020-06-18 5:08 ` Andersen, John
2020-06-18 6:59 ` Nadav Amit
2020-06-18 13:31 ` Andersen, John
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