From: Dionna Amalie Glaze <dionnaglaze@google.com>
To: Sean Christopherson <seanjc@google.com>
Cc: "Thomas Gleixner" <tglx@linutronix.de>,
"Ingo Molnar" <mingo@redhat.com>,
"Borislav Petkov" <bp@alien8.de>,
"Dave Hansen" <dave.hansen@linux.intel.com>,
x86@kernel.org, "Paolo Bonzini" <pbonzini@redhat.com>,
linux-kernel@vger.kernel.org, kvm@vger.kernel.org,
"Peter Gonda" <pgonda@google.com>,
"Jürgen Groß" <jgross@suse.com>,
"Kirill Shutemov" <kirill.shutemov@linux.intel.com>,
"Vitaly Kuznetsov" <vkuznets@redhat.com>,
"H . Peter Anvin" <hpa@zytor.com>,
"Binbin Wu" <binbin.wu@intel.com>,
"Tom Lendacky" <thomas.lendacky@amd.com>,
"Yamahata, Isaku" <isaku.yamahata@intel.com>,
"Xiang, Qinglan" <qinglan.xiang@intel.com>,
"Xu, Min M" <min.m.xu@intel.com>
Subject: Re: [PATCH 0/2] x86/kvm: Force legacy PCI hole as WB under SNP/TDX
Date: Sat, 1 Feb 2025 06:25:34 -0800 [thread overview]
Message-ID: <CAAH4kHY-Gt_6=cGL1VNsgow+XX_3wr_GxRE9hWbHomu+CaAgpw@mail.gmail.com> (raw)
In-Reply-To: <20250201005048.657470-1-seanjc@google.com>
On Fri, Jan 31, 2025 at 4:50 PM Sean Christopherson <seanjc@google.com> wrote:
>
> Attempt to hack around the SNP/TDX guest MTRR disaster by hijacking
> x86_platform.is_untracked_pat_range() to force the legacy PCI hole, i.e.
> memory from TOLUD => 4GiB, as unconditionally writeback.
>
> TDX in particular has created an impossible situation with MTRRs. Because
> TDX disallows toggling CR0.CD, TDX enabling decided the easiest solution
> was to ignore MTRRs entirely (because omitting CR0.CD write is obviously
> too simple).
>
> Unfortunately, under KVM at least, the kernel subtly relies on MTRRs to
> make ACPI play nice with device drivers. ACPI tries to map ranges it finds
> as WB, which in turn prevents device drivers from mapping device memory as
> WC/UC-.
>
> For the record, I hate this hack. But it's the safest approach I can come
> up with. E.g. forcing ioremap() to always use WB scares me because it's
> possible, however unlikely, that the kernel could try to map non-emulated
> memory (that is presented as MMIO to the guest) as WC/UC-, and silently
> forcing those mappings to WB could do weird things.
>
> My initial thought was to effectively revert the offending commit and
> skip the cache disabling/enabling, i.e. the problematic CR0.CD toggling,
> but unfortunately OVMF/EDKII has also added code to skip MTRR setup. :-(
>
EDK2 has a bug tracker. Maybe this is still fixable on Intel's end.
Adding Qinglan, Isaku, and Min to comment.
> Sean Christopherson (2):
> x86/mtrr: Return success vs. "failure" from guest_force_mtrr_state()
> x86/kvm: Override low memory above TOLUD to WB when MTRRs are forced
> WB
>
> arch/x86/include/asm/mtrr.h | 5 +++--
> arch/x86/kernel/cpu/mtrr/generic.c | 11 +++++++----
> arch/x86/kernel/kvm.c | 31 ++++++++++++++++++++++++++++--
> 3 files changed, 39 insertions(+), 8 deletions(-)
>
>
> base-commit: fd8c09ad0d87783b9b6a27900d66293be45b7bad
> --
> 2.48.1.362.g079036d154-goog
>
--
-Dionna Glaze, PhD, CISSP, CCSP (she/her)
next prev parent reply other threads:[~2025-02-01 14:25 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-01 0:50 [PATCH 0/2] x86/kvm: Force legacy PCI hole as WB under SNP/TDX Sean Christopherson
2025-02-01 0:50 ` [PATCH 1/2] x86/mtrr: Return success vs. "failure" from guest_force_mtrr_state() Sean Christopherson
2025-02-01 0:50 ` [PATCH 2/2] x86/kvm: Override low memory above TOLUD to WB when MTRRs are forced WB Sean Christopherson
2025-02-01 14:25 ` Dionna Amalie Glaze [this message]
2025-02-03 18:14 ` [PATCH 0/2] x86/kvm: Force legacy PCI hole as WB under SNP/TDX Edgecombe, Rick P
2025-02-03 20:33 ` Sean Christopherson
2025-02-03 23:01 ` Edgecombe, Rick P
2025-02-04 0:27 ` Sean Christopherson
2025-02-05 3:51 ` Edgecombe, Rick P
2025-02-05 7:49 ` Xu, Min M
2025-02-10 15:29 ` Binbin Wu
2025-07-08 14:24 ` Nikolay Borisov
-- strict thread matches above, loose matches on Subject: below --
2025-07-09 16:54 Jianxiong Gao
2025-07-14 9:06 ` Binbin Wu
2025-07-14 11:24 ` Nikolay Borisov
2025-07-15 2:53 ` Binbin Wu
2025-07-16 9:51 ` Binbin Wu
2025-07-23 14:34 ` Sean Christopherson
2025-07-24 3:16 ` Binbin Wu
2025-07-28 15:33 ` Sean Christopherson
2025-07-30 7:34 ` Binbin Wu
2025-08-15 23:55 ` Korakit Seemakhupt
2025-08-18 11:07 ` Binbin Wu
2025-08-20 3:07 ` Vishal Annapurve
2025-08-20 10:03 ` Binbin Wu
2025-08-20 11:13 ` Binbin Wu
2025-08-20 17:56 ` Sean Christopherson
2025-08-21 3:30 ` Binbin Wu
2025-08-21 5:23 ` Binbin Wu
2025-08-21 6:02 ` Jürgen Groß
2025-08-21 15:27 ` Sean Christopherson
2025-08-28 0:07 ` Sean Christopherson
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