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AJvYcCU1M7dX6UJlzzlZV8TFjJon1qyKR8+xT2XQtnWqbsz01BBwNCVYv89MCOdOTUlUSAJ2EnU=@vger.kernel.org X-Gm-Message-State: AOJu0YyzQXe7Vbb+kj/RfIxr4b4lzrqRRNalw3FtR9yejOb/I/3r//+1 +hZAJIZ1X1LWGPd3u8gdO7HepTr0W33qiRVcdNALP4p2kA37SRx+npkqxG9LnSZ6Xxc8rfrBj7q /6INtlKOaRIvQQZOSUHE3+TCNf0INef9M/5k118HI6K0trHKZwOAX X-Gm-Gg: ASbGnctc6nXPO8r34eAQL+7DDiZCuXodJuLSfNVdTxgNLmiWo8sZ2YGKVTSMXaVFYA6 hJ4EXulkwy20jgqfIDKchYSCJopbOW/9FeGhb8nnqFuXGofNQ/ViQEvBSJ31++UxbbMJQsOHKTD lCR2fOJCXyjQvrHwE7KQN+jKU6m91Qz4zuTd6tY7UAUZpYufNhemUMHtsjdD4WiptwFNMoIrpUL 7IHNUJW X-Google-Smtp-Source: AGHT+IEOqS8YGgVoprY+8f3pC+3mkVKAq8JUCoZfCHkL1OAyGAf9GO3LLl24tZ/Rk5tS5g9YXKMA+WXBYy2KvEy5e+c= X-Received: by 2002:a05:6e02:3b85:b0:3e2:a868:8bfc with SMTP id e9e14a558f8ab-3e2a8689009mr128348475ab.17.1753156537299; Mon, 21 Jul 2025 20:55:37 -0700 (PDT) Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20250721-pmu_event_info-v4-0-ac76758a4269@rivosinc.com> <20250721-pmu_event_info-v4-4-ac76758a4269@rivosinc.com> In-Reply-To: <20250721-pmu_event_info-v4-4-ac76758a4269@rivosinc.com> From: Anup Patel Date: Tue, 22 Jul 2025 09:25:26 +0530 X-Gm-Features: Ac12FXwLvJgSGjfrNWw90BLHUksAPu_rJedadgUcf1wkEVZ7pdyL3Xk4uR_QcQg Message-ID: Subject: Re: [PATCH v4 4/9] drivers/perf: riscv: Implement PMU event info function To: Atish Patra Cc: Will Deacon , Mark Rutland , Paul Walmsley , Palmer Dabbelt , Mayuresh Chitale , linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Tue, Jul 22, 2025 at 8:45=E2=80=AFAM Atish Patra w= rote: > > With the new SBI PMU event info function, we can query the availability > of the all standard SBI PMU events at boot time with a single ecall. > This improves the bootime by avoiding making an SBI call for each > standard PMU event. Since this function is defined only in SBI v3.0, > invoke this only if the underlying SBI implementation is v3.0 or higher. > > Signed-off-by: Atish Patra LGTM. Reviewed-by: Anup Patel Regards, Anup > --- > arch/riscv/include/asm/sbi.h | 9 ++++++ > drivers/perf/riscv_pmu_sbi.c | 69 ++++++++++++++++++++++++++++++++++++++= ++++++ > 2 files changed, 78 insertions(+) > > diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h > index b0c41ef56968..5ca7cebc13cc 100644 > --- a/arch/riscv/include/asm/sbi.h > +++ b/arch/riscv/include/asm/sbi.h > @@ -136,6 +136,7 @@ enum sbi_ext_pmu_fid { > SBI_EXT_PMU_COUNTER_FW_READ, > SBI_EXT_PMU_COUNTER_FW_READ_HI, > SBI_EXT_PMU_SNAPSHOT_SET_SHMEM, > + SBI_EXT_PMU_EVENT_GET_INFO, > }; > > union sbi_pmu_ctr_info { > @@ -159,6 +160,14 @@ struct riscv_pmu_snapshot_data { > u64 reserved[447]; > }; > > +struct riscv_pmu_event_info { > + u32 event_idx; > + u32 output; > + u64 event_data; > +}; > + > +#define RISCV_PMU_EVENT_INFO_OUTPUT_MASK 0x01 > + > #define RISCV_PMU_RAW_EVENT_MASK GENMASK_ULL(47, 0) > #define RISCV_PMU_PLAT_FW_EVENT_MASK GENMASK_ULL(61, 0) > /* SBI v3.0 allows extended hpmeventX width value */ > diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c > index 7331808b1192..433d122f1f41 100644 > --- a/drivers/perf/riscv_pmu_sbi.c > +++ b/drivers/perf/riscv_pmu_sbi.c > @@ -299,6 +299,66 @@ static struct sbi_pmu_event_data pmu_cache_event_map= [PERF_COUNT_HW_CACHE_MAX] > }, > }; > > +static int pmu_sbi_check_event_info(void) > +{ > + int num_events =3D ARRAY_SIZE(pmu_hw_event_map) + PERF_COUNT_HW_C= ACHE_MAX * > + PERF_COUNT_HW_CACHE_OP_MAX * PERF_COUNT_HW_CACHE= _RESULT_MAX; > + struct riscv_pmu_event_info *event_info_shmem; > + phys_addr_t base_addr; > + int i, j, k, result =3D 0, count =3D 0; > + struct sbiret ret; > + > + event_info_shmem =3D kcalloc(num_events, sizeof(*event_info_shmem= ), GFP_KERNEL); > + if (!event_info_shmem) > + return -ENOMEM; > + > + for (i =3D 0; i < ARRAY_SIZE(pmu_hw_event_map); i++) > + event_info_shmem[count++].event_idx =3D pmu_hw_event_map[= i].event_idx; > + > + for (i =3D 0; i < ARRAY_SIZE(pmu_cache_event_map); i++) { > + for (j =3D 0; j < ARRAY_SIZE(pmu_cache_event_map[i]); j++= ) { > + for (k =3D 0; k < ARRAY_SIZE(pmu_cache_event_map[= i][j]); k++) > + event_info_shmem[count++].event_idx =3D > + pmu_cache_event_m= ap[i][j][k].event_idx; > + } > + } > + > + base_addr =3D __pa(event_info_shmem); > + if (IS_ENABLED(CONFIG_32BIT)) > + ret =3D sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_EVENT_GET_INFO= , lower_32_bits(base_addr), > + upper_32_bits(base_addr), count, 0, 0, 0)= ; > + else > + ret =3D sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_EVENT_GET_INFO= , base_addr, 0, > + count, 0, 0, 0); > + if (ret.error) { > + result =3D -EOPNOTSUPP; > + goto free_mem; > + } > + > + for (i =3D 0; i < ARRAY_SIZE(pmu_hw_event_map); i++) { > + if (!(event_info_shmem[i].output & RISCV_PMU_EVENT_INFO_O= UTPUT_MASK)) > + pmu_hw_event_map[i].event_idx =3D -ENOENT; > + } > + > + count =3D ARRAY_SIZE(pmu_hw_event_map); > + > + for (i =3D 0; i < ARRAY_SIZE(pmu_cache_event_map); i++) { > + for (j =3D 0; j < ARRAY_SIZE(pmu_cache_event_map[i]); j++= ) { > + for (k =3D 0; k < ARRAY_SIZE(pmu_cache_event_map[= i][j]); k++) { > + if (!(event_info_shmem[count].output & > + RISCV_PMU_EVENT_INFO_OUTPUT_MASK)) > + pmu_cache_event_map[i][j][k].even= t_idx =3D -ENOENT; > + count++; > + } > + } > + } > + > +free_mem: > + kfree(event_info_shmem); > + > + return result; > +} > + > static void pmu_sbi_check_event(struct sbi_pmu_event_data *edata) > { > struct sbiret ret; > @@ -316,6 +376,15 @@ static void pmu_sbi_check_event(struct sbi_pmu_event= _data *edata) > > static void pmu_sbi_check_std_events(struct work_struct *work) > { > + int ret; > + > + if (sbi_v3_available) { > + ret =3D pmu_sbi_check_event_info(); > + if (ret) > + pr_err("pmu_sbi_check_event_info failed with erro= r %d\n", ret); > + return; > + } > + > for (int i =3D 0; i < ARRAY_SIZE(pmu_hw_event_map); i++) > pmu_sbi_check_event(&pmu_hw_event_map[i]); > > > -- > 2.43.0 >