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AJvYcCXIyM1HE10vs+Xr6ajyJtPzLJYazzpQZNkyRWss40SDLAIegEiXT4R1Oi72dBJJyx6BRa0=@vger.kernel.org X-Gm-Message-State: AOJu0YwVXGnTxYH0iOOB6aluy8/EhKJnNP/WnfzwWnZKcEWg1+4E1Vdz V+HFcYz3iXSmwrYENufPgydsAwDxQ2MKxUrnBB5euaebnYB93qak2BB4dOz49Xx9vCHnf3e2BWg uGsQkybzeyN7z2FEF1fnGF9X5QARmfJr8clbB8ce0pQ== X-Gm-Gg: ASbGnct9HfzK8hS005CD+6SLgqWxHevjXhsb3NY8wakkZcXoeA4p83zMh68ihZBOBUy 6VshkPTsJWZCPdnV2Lc7LvEHE1zyRzVaOpJG3FpR5vwyW3cUQJwEwJBMAMvlyrmOw6gGQ3CpJ5Y lL4oxm704+r1qcSFnJWdhcKvfwQvudK0b6ZHcFFouR0WFT13tAwHaGjqvGf1sDLUeGewO3YiWgZ ZnQRzog X-Google-Smtp-Source: AGHT+IEzXZtRTpqZPP5g7x2Fm91kPpdZS5/X5V/55yjLcJ8BQVVYt3sRPxAm7hdiFuIt8kIDsDR0IpWsd9pUjol0rkY= X-Received: by 2002:a05:6e02:3045:b0:3e0:4f66:310a with SMTP id e9e14a558f8ab-3e282e868cbmr102473895ab.16.1752813586416; Thu, 17 Jul 2025 21:39:46 -0700 (PDT) Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20250522-pmu_event_info-v3-0-f7bba7fd9cfe@rivosinc.com> <20250522-pmu_event_info-v3-5-f7bba7fd9cfe@rivosinc.com> In-Reply-To: <20250522-pmu_event_info-v3-5-f7bba7fd9cfe@rivosinc.com> From: Anup Patel Date: Fri, 18 Jul 2025 10:09:34 +0530 X-Gm-Features: Ac12FXz48gZhuRL6l_A_d2ML5HT5uyFhLTVui-Isq6ALvDwU7Ubg6PFae_bdCbw Message-ID: Subject: Re: [PATCH v3 5/9] drivers/perf: riscv: Export PMU event info function To: Atish Patra Cc: Will Deacon , Mark Rutland , Paul Walmsley , Palmer Dabbelt , Mayuresh Chitale , linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Fri, May 23, 2025 at 12:33=E2=80=AFAM Atish Patra = wrote: > > The event mapping function can be used in event info function to find out > the corresponding SBI PMU event encoding during the get_event_info functi= on > as well. Refactor and export it so that it can be invoked from kvm and > internal driver. > > Signed-off-by: Atish Patra > --- > drivers/perf/riscv_pmu_sbi.c | 124 ++++++++++++++++++++++-------------= ------ > include/linux/perf/riscv_pmu.h | 2 + > 2 files changed, 69 insertions(+), 57 deletions(-) > > diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c > index 33d8348bf68a..f5d3db6dba18 100644 > --- a/drivers/perf/riscv_pmu_sbi.c > +++ b/drivers/perf/riscv_pmu_sbi.c > @@ -100,6 +100,7 @@ static unsigned int riscv_pmu_irq; > /* Cache the available counters in a bitmask */ > static unsigned long cmask; > > +static int pmu_event_find_cache(u64 config); > struct sbi_pmu_event_data { > union { > union { > @@ -411,6 +412,71 @@ static bool pmu_sbi_ctr_is_fw(int cidx) > return (info->type =3D=3D SBI_PMU_CTR_TYPE_FW) ? true : false; > } > > +int riscv_pmu_get_event_info(u32 type, u64 config, u64 *econfig) > +{ > + int ret =3D -ENOENT; > + > + switch (type) { > + case PERF_TYPE_HARDWARE: > + if (config >=3D PERF_COUNT_HW_MAX) > + return -EINVAL; > + ret =3D pmu_hw_event_map[config].event_idx; > + break; > + case PERF_TYPE_HW_CACHE: > + ret =3D pmu_event_find_cache(config); > + break; > + case PERF_TYPE_RAW: > + /* > + * As per SBI v0.3 specification, > + * -- the upper 16 bits must be unused for a hardware ra= w event. > + * As per SBI v3.0 specification, > + * -- the upper 8 bits must be unused for a hardware raw= event. > + * Bits 63:62 are used to distinguish between raw events > + * 00 - Hardware raw event > + * 10 - SBI firmware events > + * 11 - Risc-V platform specific firmware event > + */ > + switch (config >> 62) { > + case 0: > + if (sbi_v3_available) { > + /* Return error any bits [56-63] is set as it is= not allowed by the spec */ > + if (!(config & ~RISCV_PMU_RAW_EVENT_V2_MA= SK)) { > + if (econfig) > + *econfig =3D config & RIS= CV_PMU_RAW_EVENT_V2_MASK; > + ret =3D RISCV_PMU_RAW_EVENT_V2_ID= X; > + } > + /* Return error any bits [48-63] is set as it is= not allowed by the spec */ > + } else if (!(config & ~RISCV_PMU_RAW_EVENT_MASK))= { > + if (econfig) > + *econfig =3D config & RISCV_PMU_R= AW_EVENT_MASK; > + ret =3D RISCV_PMU_RAW_EVENT_IDX; > + } > + break; > + case 2: > + ret =3D (config & 0xFFFF) | (SBI_PMU_EVENT_TYPE_F= W << 16); > + break; > + case 3: > + /* > + * For Risc-V platform specific firmware events > + * Event code - 0xFFFF > + * Event data - raw event encoding > + */ > + ret =3D SBI_PMU_EVENT_TYPE_FW << 16 | RISCV_PLAT_= FW_EVENT; > + if (econfig) > + *econfig =3D config & RISCV_PMU_PLAT_FW_E= VENT_MASK; > + break; > + default: > + break; > + } > + break; > + default: > + break; > + } > + > + return ret; > +} > +EXPORT_SYMBOL_GPL(riscv_pmu_get_event_info); > + > /* > * Returns the counter width of a programmable counter and number of har= dware > * counters. As we don't support heterogeneous CPUs yet, it is okay to j= ust > @@ -576,7 +642,6 @@ static int pmu_sbi_event_map(struct perf_event *event= , u64 *econfig) > { > u32 type =3D event->attr.type; > u64 config =3D event->attr.config; > - int ret =3D -ENOENT; > > /* > * Ensure we are finished checking standard hardware events for > @@ -584,62 +649,7 @@ static int pmu_sbi_event_map(struct perf_event *even= t, u64 *econfig) > */ > flush_work(&check_std_events_work); > > - switch (type) { > - case PERF_TYPE_HARDWARE: > - if (config >=3D PERF_COUNT_HW_MAX) > - return -EINVAL; > - ret =3D pmu_hw_event_map[event->attr.config].event_idx; > - break; > - case PERF_TYPE_HW_CACHE: > - ret =3D pmu_event_find_cache(config); > - break; > - case PERF_TYPE_RAW: > - /* > - * As per SBI v0.3 specification, > - * -- the upper 16 bits must be unused for a hardware ra= w event. > - * As per SBI v3.0 specification, > - * -- the upper 8 bits must be unused for a hardware raw= event. > - * Bits 63:62 are used to distinguish between raw events > - * 00 - Hardware raw event > - * 10 - SBI firmware events > - * 11 - Risc-V platform specific firmware event > - */ > - > - switch (config >> 62) { > - case 0: > - if (sbi_v3_available) { > - /* Return error any bits [56-63] is set as it is= not allowed by the spec */ > - if (!(config & ~RISCV_PMU_RAW_EVENT_V2_MA= SK)) { > - *econfig =3D config & RISCV_PMU_R= AW_EVENT_V2_MASK; > - ret =3D RISCV_PMU_RAW_EVENT_V2_ID= X; > - } > - /* Return error any bits [48-63] is set as it is= not allowed by the spec */ > - } else if (!(config & ~RISCV_PMU_RAW_EVENT_MASK))= { > - *econfig =3D config & RISCV_PMU_RAW_EVENT= _MASK; > - ret =3D RISCV_PMU_RAW_EVENT_IDX; > - } > - break; > - case 2: > - ret =3D (config & 0xFFFF) | (SBI_PMU_EVENT_TYPE_F= W << 16); > - break; > - case 3: > - /* > - * For Risc-V platform specific firmware events > - * Event code - 0xFFFF > - * Event data - raw event encoding > - */ > - ret =3D SBI_PMU_EVENT_TYPE_FW << 16 | RISCV_PLAT_= FW_EVENT; > - *econfig =3D config & RISCV_PMU_PLAT_FW_EVENT_MAS= K; > - break; > - default: > - break; > - } > - break; > - default: > - break; > - } > - > - return ret; > + return riscv_pmu_get_event_info(type, config, econfig); > } > > static void pmu_sbi_snapshot_free(struct riscv_pmu *pmu) > diff --git a/include/linux/perf/riscv_pmu.h b/include/linux/perf/riscv_pm= u.h > index 701974639ff2..4a5e3209c473 100644 > --- a/include/linux/perf/riscv_pmu.h > +++ b/include/linux/perf/riscv_pmu.h > @@ -91,6 +91,8 @@ struct riscv_pmu *riscv_pmu_alloc(void); > int riscv_pmu_get_hpm_info(u32 *hw_ctr_width, u32 *num_hw_ctr); > #endif > > +int riscv_pmu_get_event_info(u32 type, u64 config, u64 *econfig); > + > #endif /* CONFIG_RISCV_PMU */ We will see compile/link errors for users of riscv_pmu_get_event_info() if CONFIG_RISCV_PMU_SBI is not defined. Am I missing anything > > #endif /* _RISCV_PMU_H */ > > -- > 2.43.0 > Regards, Anup