From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Liwen Wu (liwwu)" Subject: Re: How to enable Pause Loop Exiting (PLE)? Date: Mon, 9 Jun 2014 21:04:54 +0000 Message-ID: References: <201406091152083051957@sangfor.com> <201406091424598514306@sangfor.com> <201406091516447118444@sangfor.com> Mime-Version: 1.0 Content-Type: text/plain; charset=Windows-1252 Content-Transfer-Encoding: QUOTED-PRINTABLE Cc: KVM To: Jidong Xiao , Zhang Haoyu Return-path: Received: from rcdn-iport-2.cisco.com ([173.37.86.73]:28484 "EHLO rcdn-iport-2.cisco.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751158AbaFIVOZ convert rfc822-to-8bit (ORCPT ); Mon, 9 Jun 2014 17:14:25 -0400 In-Reply-To: Content-Language: en-US Content-ID: <1FCC4D5C2178FF46BA81E11E71440136@emea.cisco.com> Sender: kvm-owner@vger.kernel.org List-ID: On 6/9/14 1:27 PM, "Jidong Xiao" wrote: >On Mon, Jun 9, 2014 at 3:16 AM, Zhang Haoyu wrot= e: >>>>>>Hi, >>>>>> >>>>>>I am using this tool for querying VMX capabilities. >>>>>> >>>>>>http://git.qemu.org/?p=3Dqemu.git;a=3Dblob_plain;f=3Dscripts/kvm/= vmxcap;hb=3D >>>>>>HEAD >>>>>> >>>>>>And it shows as below that pause-loop exiting is not enabled. My >>>>>>kernel is 3.14. >>>>>> >>>>>>secondary processor-based controls >>>>>> Virtualize APIC accesses yes >>>>>> Enable EPT yes >>>>>> Descriptor-table exiting yes >>>>>> Enable RDTSCP yes >>>>>> Virtualize x2APIC mode yes >>>>>> Enable VPID yes >>>>>> WBINVD exiting yes >>>>>> Unrestricted guest no >>>>>> APIC register emulation no >>>>>> Virtual interrupt delivery no >>>>>> PAUSE-loop exiting no >>>>>> RDRAND exiting no >>>>>> Enable INVPCID no >>>>>> Enable VM functions no >>>>>> VMCS shadowing no >>>>>> EPT-violation #VE no >>>>>> >>>>>>What shall I do if I wish to enable PLE? I have also tried this: >>>>>> >>>>> From above info, your physical cpu dose not support ple feature, >>>>> if you want to enable ple, your cpu must support ple feature, and >>>>>'PAUSE exiting' must be 0-settting, 'PAUSE-loop exiting' must be >>>>>1-setting. >>>>> And, kvm-intel module will enable ple as default if your cpu supp= ort >>>>>ple feature. >>>>> >>>>Hi, Haoyu, >>>> >>>>I have another machine, in which Pause Loop Exiting is showing yes, >>>>but PAUSE Exiting is also showing yes, see below, but you said PAUS= E >>>>exiting must be 0 setting, so what shall I do? Is PLE enabled or no= t? >>>> >>>check /sys/module/kvm_intel/parameters/ple_gap, if non-zero(>0), ple= is >>>enabled, zero means ple is disabled. >>> >> Sorry, even /sys/module/kvm_intel/parameters/ple_gap is non-zero, it >>cannot say ple is enabled, it only means 'PAUSE-loop exiting' is >>1-setting, >> but the 'PAUSE-loop exiting' is ignored if 'PAUSE exiting' is >>1-settting. >> But >> Below words is from the intel 64 and IA-32 Architectures Software >>Developer=B9s Manual Volume 3C, >> =80 PAUSE.The behavior of each of this instruction depends on CPL an= d the >>settings of the =B3PAUSE exiting=B2 and >> =B3PAUSE-loop exiting=B2 VM-execution controls: >> =8B CPL=3D 0. >> =80 If the =B3PAUSE exiting=B2 and =B3PAUSE-loop exiting=B2 VM-e= xecution >>controls are both 0, the PAUSE >> instruction executes normally. >> =80 If the =B3PAUSE exiting=B2 VM-execution control is 1, the PA= USE >>instruction causes a VM exit (the =B3PAUSEloop >> exiting=B2 VM-execution control is ignored if CPL =3D 0 and th= e >>=B3PAUSE exiting=B2 VM-execution control >> is 1). >> =80 If the =B3PAUSE exiting=B2 VM-execution control is 0 and the >>=B3PAUSE-loop exiting=B2 VM-execution control is >> 1, the following treatment applies. >> The processor determines the amount of time between this >>execution of PAUSE and the previous >> execution of PAUSE at CPL 0. If this amount of time exceeds th= e >>value of the VM-execution control field >> PLE_Gap, the processor considers this execution to be the firs= t >>execution of PAUSE in a loop. (It also >> does so for the first execution of PAUSE at CPL 0 after VM ent= ry.) >> Otherwise, the processor determines the amount of time since t= he >>most recent execution of PAUSE that >> was considered to be the first in a loop. If this amount of ti= me >>exceeds the value of the VM-execution >> control field PLE_Window, a VM exit occurs. >> For purposes of these computations, time is measured based on = a >>counter that runs at the same rate as >> the timestamp counter (TSC). >> =8B CPL> 0. >> =80 If the =B3PAUSE exiting=B2 VM-execution control is 0, the PA= USE >>instruction executes normally. >> =80 If the =B3PAUSE exiting=B2 VM-execution control is 1, the PA= USE >>instruction causes a VM exit. >> The =B3PAUSE-loop exiting=B2 VM-execution control is ignored if = CPL > 0. >> >Thanks. So PLE is still not enabled on my machine? Then how to let >"PAUSE Exiting" to be 0-setting? > >-Jidong > >>>>primary processor-based controls >>>> Interrupt window exiting yes >>>> Use TSC offsetting yes >>>> HLT exiting yes >>>> INVLPG exiting yes >>>> MWAIT exiting yes >>>> RDPMC exiting yes >>>> RDTSC exiting yes >>>> CR3-load exiting default >>>> CR3-store exiting default >>>> CR8-load exiting yes >>>> CR8-store exiting yes >>>> Use TPR shadow yes >>>> NMI-window exiting yes >>>> MOV-DR exiting yes >>>> Unconditional I/O exiting yes >>>> Use I/O bitmaps yes >>>> Monitor trap flag yes >>>> Use MSR bitmaps yes >>>> MONITOR exiting yes >>>> PAUSE exiting yes >>>> Activate secondary control yes >>>>secondary processor-based controls >>>> Virtualize APIC accesses yes >>>> Enable EPT yes >>>> Descriptor-table exiting yes >>>> Enable RDTSCP yes >>>> Virtualize x2APIC mode yes >>>> Enable VPID yes >>>> WBINVD exiting yes >>>> Unrestricted guest yes >>>> APIC register emulation no >>>> Virtual interrupt delivery no >>>> PAUSE-loop exiting yes >>>> RDRAND exiting no >>>> Enable INVPCID no >>>> Enable VM functions no >>>> VMCS shadowing no >>>> EPT-violation #VE no >-- >To unsubscribe from this list: send the line "unsubscribe kvm" in >the body of a message to majordomo@vger.kernel.org >More majordomo info at http://vger.kernel.org/majordomo-info.html