[kvm-unit-tests v3 13/13] powerpc/sprs: Test hypervisor registers on powernv machine

Nicholas Piggin
2023-03-27T12:46:32Z

This enables HV privilege registers to be tested with the powernv
machine.

Acked-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
powerpc/sprs.c | 33 +++++++++++++++++++++++++--------
1 file changed, 25 insertions(+), 8 deletions(-)

diff --git a/powerpc/sprs.c b/powerpc/sprs.c
index d566420..07a4e75 100644
--- a/powerpc/sprs.c
+++ b/powerpc/sprs.c
@@ -199,16 +199,16 @@ static const struct spr sprs_power_common[1024] = {
[190] = {"HFSCR", 64, HV_RW, },
[256] = {"VRSAVE", 32, RW, },
[259] = {"SPRG3", 64, RO, },
-[284] = {"TBL", 32, HV_WO, },
-[285] = {"TBU", 32, HV_WO, },
-[286] = {"TBU40", 64, HV_WO, },
+[284] = {"TBL", 32, HV_WO, }, /* Things can go a bit wonky with */
+[285] = {"TBU", 32, HV_WO, }, /* Timebase changing. Should save */
+[286] = {"TBU40", 64, HV_WO, }, /* and restore it. */
[304] = {"HSPRG0", 64, HV_RW, },
[305] = {"HSPRG1", 64, HV_RW, },
[306] = {"HDSISR", 32, HV_RW, SPR_INT, },
[307] = {"HDAR", 64, HV_RW, SPR_INT, },
[308] = {"SPURR", 64, HV_RW | OS_RO, SPR_ASYNC, },
[309] = {"PURR", 64, HV_RW | OS_RO, SPR_ASYNC, },
-[313] = {"HRMOR", 64, HV_RW, },
+[313] = {"HRMOR", 64, HV_RW, SPR_HARNESS, }, /* Harness can't cope with HRMOR changing */
[314] = {"HSRR0", 64, HV_RW, SPR_INT, },
[315] = {"HSRR1", 64, HV_RW, SPR_INT, },
[318] = {"LPCR", 64, HV_RW, },
@@ -306,7 +306,7 @@ static const struct spr sprs_power9_10[1024] = {
[921] = {"TSCR", 32, HV_RW, },
[922] = {"TTR", 64, HV_RW, },
[1006]= {"TRACE", 64, WO, },
-[1008]= {"HID", 64, HV_RW, },
+[1008]= {"HID", 64, HV_RW, SPR_HARNESS, }, /* At least HILE would be unhelpful to change */
};

/* This covers POWER8 and POWER9 PMUs */
@@ -350,6 +350,22 @@ static const struct spr sprs_power10_pmu[1024] = {

static struct spr sprs[1024];

+static bool spr_read_perms(int spr)
+{
+ if (machine_is_powernv())
+ return !!(sprs[spr].access & SPR_HV_READ);
+ else
+ return !!(sprs[spr].access & SPR_OS_READ);
+}
+
+static bool spr_write_perms(int spr)
+{
+ if (machine_is_powernv())
+ return !!(sprs[spr].access & SPR_HV_WRITE);
+ else
+ return !!(sprs[spr].access & SPR_OS_WRITE);
+}
+
static void setup_sprs(void)
{
uint32_t pvr = mfspr(287); /* Processor Version Register */
@@ -466,7 +482,7 @@ static void get_sprs(uint64_t *v)
int i;

for (i = 0; i < 1024; i++) {
- if (!(sprs[i].access & SPR_OS_READ))
+ if (!spr_read_perms(i))
continue;
v[i] = __mfspr(i);
}
@@ -477,8 +493,9 @@ static void set_sprs(uint64_t val)
int i;

for (i = 0; i < 1024; i++) {
- if (!(sprs[i].access & SPR_OS_WRITE))
+ if (!spr_write_perms(i))
continue;
+
if (sprs[i].type & SPR_HARNESS)
continue;
if (!strcmp(sprs[i].name, "MMCR0")) {
@@ -550,7 +567,7 @@ int main(int argc, char **argv)
for (i = 0; i < 1024; i++) {
bool pass = true;

- if (!(sprs[i].access & SPR_OS_READ))
+ if (!spr_read_perms(i))
continue;

if (sprs[i].width == 32) {
--
2.37.2