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[110.175.65.7]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7024967ae05sm7161080b3a.157.2024.06.04.18.07.01 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 04 Jun 2024 18:07:03 -0700 (PDT) Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Wed, 05 Jun 2024 11:06:57 +1000 Message-Id: Cc: "Laurent Vivier" , "Andrew Jones" , , Subject: Re: [kvm-unit-tests PATCH v9 22/31] powerpc: Add MMU support From: "Nicholas Piggin" To: "Thomas Huth" X-Mailer: aerc 0.17.0 References: <20240504122841.1177683-1-npiggin@gmail.com> <20240504122841.1177683-23-npiggin@gmail.com> <75adb602-7ccc-4dcd-916e-5f79fcd1cdd3@redhat.com> In-Reply-To: <75adb602-7ccc-4dcd-916e-5f79fcd1cdd3@redhat.com> On Tue Jun 4, 2024 at 5:30 PM AEST, Thomas Huth wrote: > On 04/05/2024 14.28, Nicholas Piggin wrote: > > Add support for radix MMU, 4kB and 64kB pages. > >=20 > > This also adds MMU interrupt test cases, and runs the interrupts > > test entirely with MMU enabled if it is available (aside from > > machine check tests). > >=20 > > Acked-by: Andrew Jones (configure changes) > > Signed-off-by: Nicholas Piggin > > --- > ... > > diff --git a/lib/ppc64/mmu.c b/lib/ppc64/mmu.c > > new file mode 100644 > > index 000000000..5307cd862 > > --- /dev/null > > +++ b/lib/ppc64/mmu.c > > @@ -0,0 +1,281 @@ > > +/* SPDX-License-Identifier: GPL-2.0-only */ > > +/* > > + * Radix MMU support > > + * > > + * Copyright (C) 2024, IBM Inc, Nicholas Piggin > > + * > > + * Derived from Linux kernel MMU code. > > + */ > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +#include "alloc_page.h" > > +#include "vmalloc.h" > > +#include > > +#include > > + > > +#include > > + > > +static pgd_t *identity_pgd; > > + > > +bool vm_available(void) > > +{ > > + return cpu_has_radix; > > +} > > + > > +bool mmu_enabled(void) > > +{ > > + return current_cpu()->pgtable !=3D NULL; > > +} > > + > > +void mmu_enable(pgd_t *pgtable) > > +{ > > + struct cpu *cpu =3D current_cpu(); > > + > > + if (!pgtable) > > + pgtable =3D identity_pgd; > > + > > + cpu->pgtable =3D pgtable; > > + > > + mtmsr(mfmsr() | (MSR_IR|MSR_DR)); > > +} > > + > > +void mmu_disable(void) > > +{ > > + struct cpu *cpu =3D current_cpu(); > > + > > + cpu->pgtable =3D NULL; > > + > > + mtmsr(mfmsr() & ~(MSR_IR|MSR_DR)); > > +} > > + > > +static inline void tlbie(unsigned long rb, unsigned long rs, int ric, = int prs, int r) > > +{ > > + asm volatile(".machine push ; .machine power9; ptesync ; tlbie %0,%1,= %2,%3,%4 ; eieio ; tlbsync ; ptesync ; .machine pop" :: "r"(rb), "r"(rs), "= i"(ric), "i"(prs), "i"(r) : "memory"); > > That's a very long line, please split it up after every assembly instruct= ion=20 > (using \n for new lines). > > > +} > ... > > diff --git a/powerpc/mmu.c b/powerpc/mmu.c > > new file mode 100644 > > index 000000000..fef790506 > > --- /dev/null > > +++ b/powerpc/mmu.c > > @@ -0,0 +1,283 @@ > > +/* SPDX-License-Identifier: LGPL-2.0-only */ > > +/* > > + * MMU Tests > > + * > > + * Copyright 2024 Nicholas Piggin, IBM Corp. > > + */ > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +static inline void tlbie(unsigned long rb, unsigned long rs, int ric, = int prs, int r) > > +{ > > + asm volatile(".machine push ; .machine power9; ptesync ; tlbie %0,%1,= %2,%3,%4 ; eieio ; tlbsync ; ptesync ; .machine pop" :: "r"(rb), "r"(rs), "= i"(ric), "i"(prs), "i"(r) : "memory"); > > +} > > Same function again? Maybe it could go into mmu.h instead? > > > +static inline void tlbiel(unsigned long rb, unsigned long rs, int ric,= int prs, int r) > > +{ > > + asm volatile(".machine push ; .machine power9; ptesync ; tlbiel %0,%1= ,%2,%3,%4 ; ptesync ; .machine pop" :: "r"(rb), "r"(rs), "i"(ric), "i"(prs)= , "i"(r) : "memory"); > > +} > > Please also split up the above long line. I'll try to improve the lines. > It would also be cool if you could get one of the other ppc guys at IBM t= o=20 > review this patch, since I don't have a clue about this MMU stuff at all. It would be. Thanks, Nick