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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by SJ1PEPF0000231D.mail.protection.outlook.com (10.167.242.234) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9542.4 via Frontend Transport; Fri, 16 Jan 2026 12:59:40 +0000 Received: from localhost (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Fri, 16 Jan 2026 06:59:39 -0600 Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="UTF-8" Date: Fri, 16 Jan 2026 13:59:37 +0100 Message-ID: CC: , Paolo Bonzini , "Yosry Ahmed" , Kevin Cheng Subject: Re: [kvm-unit-tests] x86: Add #PF test case for the SVM DecodeAssists feature From: Alejandro Vallejo To: Sean Christopherson X-Mailer: aerc 0.20.1 References: <20260115131739.25362-1-alejandro.garciavallejo@amd.com> <20260115164342.27736-1-alejandro.garciavallejo@amd.com> In-Reply-To: X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF0000231D:EE_|DM6PR12MB4089:EE_ X-MS-Office365-Filtering-Correlation-Id: 1309d4a9-d1c1-4f2e-dd5f-08de54ff1c84 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|30052699003|376014|82310400026|1800799024|36860700013; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jan 2026 12:59:40.3710 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1309d4a9-d1c1-4f2e-dd5f-08de54ff1c84 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF0000231D.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4089 Hi, On Thu Jan 15, 2026 at 7:32 PM CET, Sean Christopherson wrote: > +Kevin and Yosry, who are working on similar tests > > On Thu, Jan 15, 2026, Alejandro Vallejo wrote: >> Tests an intercepted #PF accesing the last (unmapped) qword of the >> virtual address space. The assist ought provides a prefetched >> code stream starting at the offending instruction. >>=20 >> This is little more than a smoke test. There's more cases not covered. >> Namely, CR/DR MOVs, INTn, INVLPG, nested PFs, and fault-on-fetch. >>=20 >> Signed-off-by: Alejandro Vallejo >> --- >> I'm not a big fan of using a literal -8ULL as "unbacked va", but I'm not >> sure how to instruct the harness to give me a hole. > > Allocate a page, then use install_pte() or install_page_prot() to create = a mapping > that will #PF. Right. It hadn't clicked for me exactly how L1 and L2 are related in the harness. So this test group runs with the L2 reusing the mappings from the = L1? > >> Likewise, some cases remain >> untested, with the interesting one (fault-on-fetch) requiring some cumbe= rsome >> setup (put the codestream in the 14 bytes leading to a non-present NPT p= age. > > Not _that_ cumbersome though. Allocate a page, install_page_prot() with = NX, > copy/write an instruction to the page, jump/call into the page. > > run_in_user_ex() makes it even easier to do that at CPL3. I didn't mean fetch as in faulted instruction, but rather the CPU hitting a missing PT as it fetches the 15 bytes of the codestream including and follo= wing the faulting instruction. That'd be... opcode_pre: mov ($not_present), %al /* #PF! */ not_present: /* page boundary */ int3; /* unmapped in the NPT */ ... where the CPU would try to fetch int3, and a bunch more bytes on VMEXIT= but fail, thus leaving insn_len as "not_present - opcode_pre" rather than 15. I= n the absence of faults the CPU always fetches as much as possible on #PF/NPT-fau= lt intercepts. A complete testcase would show the expected non-15 number as length. > > All the above said, I would rather piggyback the access test and not rein= vent the > wheel. E.g. wrap ac_test_run() a la vmx_pf_exception_test(), then interc= ept #PF > to verify the instruction information is filled as expected. We'd need t= o modify > ac_test_do_access() to record what instruction it expected to fault, but = that > shouldn't be _too_ hard, and it might even force us to improve the inscru= table > asm blob. I can see how this would be better for the simple test I have in this patch= , but it would probably overcomplicate ac_test_do_access() in the more complete version with the instruction being at the boundary of a missing page. I'll try to integrate it anyway on the off chance any other caller happens = to need it. I'm skeptical the result would look pretty, but we'll see; maybe i= t turns out alright. I'll get back to you after I find some time to play with= it. On another note, would you prefer individual tests for every single assist or does it sound ok to have this single test for the #PF case? There's no meaningful difference between #PF and NPT faults as far as the assists are concerned, and all others are implicitly covered by virtue of exit_info_1 being unconditionally copied irrespective of exit code. They are trivial to write, so it's simply a matter of the test volume you'r= e willing to have. Cheers for the feedback, Alejandro