Re: [PATCH v4 9/9] KVM: x86: LAM: Expose LAM CPUID to user space VMM

Robert Hoo
2023-02-21T14:37:05Z

On Tue, 2023-02-21 at 21:18 +0800, Binbin Wu wrote:
> On 2/21/2023 7:13 PM, Yu Zhang wrote:
> > > The special handling for LA57 is from the patch "kvm: x86: Return
> > > LA57
> > > feature based on hardware capability".
> > > https://lore.kernel.org/lkml/1548950983-18458-1-git-send-email-yu.c.zhang@linux.intel.com/
> > >
> > > The reason is host kernel may disable 5-level paging using
> > > cmdline parameter
> > > 'no5lvl', and it will clear the feature bit for LA57 in
> > > boot_cpu_data.
> > > boot_cpu_data is queried in kvm_set_cpu_caps to derive kvm cpu
> > > cap masks.
> > >
> > > " VMs can still benefit from extended linear address width, e.g.
> > > to enhance
> > > features like ASLR" even when host doesn't use 5-level paging.
> > > So, the patch sets LA57 based on hardware capability.
> > >
> > > I was just wondering whether LAM could be the similar case that
> > > the host
> > > disabled the feature somehow (e.g via clearcpuid), and the guest
> > > still want
> > > to use it.
> >
> > Paging modes in root & non-root are orthogonal, so should LAM.
>
> Agree.
>
Understand

In
https://lore.kernel.org/lkml/1548950983-18458-1-git-send-email-yu.c.zhang@linux.intel.com/
, it mentioned
"As discussed earlier, VMs can still benefit from extended linear
address width, e.g. to enhance features like ASLR. So we would like to
fix this..."

Apparently something was "discussed earlier", some request was made for
that (perhaps related to ASLR).
Read through kvm_set_cpu_caps(), such kind of handling, i.e. bypass
host/KVM and expose the feature as long as HW supports it, is exception
case.
Therefore, though LAM could be done like LA57, I hesitate to make LAM
exception case to break existing framework, unless analogous
discussion/request for it occurs.