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[34.168.104.7]) by smtp.gmail.com with ESMTPSA id f129-20020a623887000000b0058bf2ae9694sm10265600pfa.156.2023.01.19.17.33.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Jan 2023 17:33:22 -0800 (PST) Date: Fri, 20 Jan 2023 01:33:18 +0000 From: Sean Christopherson To: Kim Phillips Cc: x86@kernel.org, Borislav Petkov , Borislav Petkov , Boris Ostrovsky , Dave Hansen , "H. Peter Anvin" , Ingo Molnar , Joao Martins , Jonathan Corbet , Konrad Rzeszutek Wilk , Paolo Bonzini , Thomas Gleixner , David Woodhouse , Greg Kroah-Hartman , Juergen Gross , Peter Zijlstra , Tony Luck , Tom Lendacky , Alexey Kardashevskiy , kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v6 2/7] x86/cpu, kvm: Add the NO_NESTED_DATA_BP feature Message-ID: References: <20230110224643.452273-1-kim.phillips@amd.com> <20230110224643.452273-4-kim.phillips@amd.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230110224643.452273-4-kim.phillips@amd.com> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On Tue, Jan 10, 2023, Kim Phillips wrote: > The "Processor ignores nested data breakpoints" feature was being > open-coded for KVM in __do_cpuid_func(). Add it to its newly added > CPUID leaf 0x80000021 EAX proper, and propagate it in kvm_set_cpu_caps() > instead. > > Also drop the bit description comments now it's more self-describing. > > Signed-off-by: Kim Phillips > --- > arch/x86/include/asm/cpufeatures.h | 3 +++ > arch/x86/kvm/cpuid.c | 8 ++++++-- > 2 files changed, 9 insertions(+), 2 deletions(-) > > diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h > index d53e13048d2e..0cd7b4afd528 100644 > --- a/arch/x86/include/asm/cpufeatures.h > +++ b/arch/x86/include/asm/cpufeatures.h > @@ -426,6 +426,9 @@ > #define X86_FEATURE_V_TSC_AUX (19*32+ 9) /* "" Virtual TSC_AUX */ > #define X86_FEATURE_SME_COHERENT (19*32+10) /* "" AMD hardware-enforced cache coherency */ > > +/* AMD-defined Extended Feature 2 EAX, CPUID level 0x80000021 (EAX), word 20 */ > +#define X86_FEATURE_NO_NESTED_DATA_BP (20*32+ 0) /* "" AMD No Nested Data Breakpoints */ > + > /* > * BUG word(s) > */ > diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c > index b14653b61470..69e433e4e9ff 100644 > --- a/arch/x86/kvm/cpuid.c > +++ b/arch/x86/kvm/cpuid.c > @@ -741,6 +741,10 @@ void kvm_set_cpu_caps(void) > 0 /* SME */ | F(SEV) | 0 /* VM_PAGE_FLUSH */ | F(SEV_ES) | > F(SME_COHERENT)); > > + kvm_cpu_cap_mask(CPUID_8000_0021_EAX, > + F(NO_NESTED_DATA_BP) > + ); > + > kvm_cpu_cap_mask(CPUID_C000_0001_EDX, > F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) | > F(ACE2) | F(ACE2_EN) | F(PHE) | F(PHE_EN) | > @@ -1222,9 +1226,9 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function) > break; > case 0x80000021: > entry->ebx = entry->ecx = entry->edx = 0; > + cpuid_entry_override(entry, CPUID_8000_0021_EAX); > /* > * Pass down these bits: > - * EAX 0 NNDBP, Processor ignores nested data breakpoints > * EAX 2 LAS, LFENCE always serializing > * EAX 6 NSCB, Null selector clear base > * > @@ -1235,7 +1239,7 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function) > * KVM doesn't support SMM_CTL. > * EAX 9 SMM_CTL MSR is not supported > */ > - entry->eax &= BIT(0) | BIT(2) | BIT(6); > + entry->eax &= BIT(2) | BIT(6); This is broken. It gets fixed by the end of the series, but between here and commit b1366f515fd6 ("x86/cpu, kvm: Add the Null Selector Clears Base feature"), the AND with open coded bits means any bits preserved/set by cpuid_entry_override() are wiped out. E.g. NO_NESTED_DATA_BP will never be advertised as of this patch. The proper way to do this is to first convert all supported bits away from magic numbers in a single patch, and then introduce newly supported bits one by one. That one patch will be larger, but I don't see a better approach. Is it too late to back this out? Not a huge deal, but it seems easy enough to clean up.