From: Conor Dooley <conor@kernel.org>
To: Andy Chiu <andy.chiu@sifive.com>
Cc: linux-riscv@lists.infradead.org, palmer@dabbelt.com,
anup@brainfault.org, atishp@atishpatra.org,
kvm-riscv@lists.infradead.org, kvm@vger.kernel.org,
vineetg@rivosinc.com, greentime.hu@sifive.com,
guoren@linux.alibaba.com,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>, Guo Ren <guoren@kernel.org>,
Vincent Chen <vincent.chen@sifive.com>,
Myrtle Shah <gatecat@ds0.me>,
Alexandre Ghiti <alexandre.ghiti@canonical.com>
Subject: Re: [PATCH -next v13 04/19] riscv: Clear vector regfile on bootup
Date: Wed, 25 Jan 2023 21:54:04 +0000 [thread overview]
Message-ID: <Y9Gk/FCFBbWC/Pyi@spud> (raw)
In-Reply-To: <20230125142056.18356-5-andy.chiu@sifive.com>
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On Wed, Jan 25, 2023 at 02:20:41PM +0000, Andy Chiu wrote:
> clear vector registers on boot if kernel supports V.
>
> Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>
> [vineetg: broke this out to a seperate patch]
> Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
But this patch didn't carry over the long list of contributors from it's
source? Seems a bit odd, that's all.
There was also an Rb from Palmer that got dropped too. Was that
intentional?
https://lore.kernel.org/linux-riscv/20220921214439.1491510-6-stillson@rivosinc.com/
Thanks,
Conor.
> ---
> arch/riscv/kernel/head.S | 23 +++++++++++++++++++++++
> 1 file changed, 23 insertions(+)
>
> diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
> index b865046e4dbb..ea803c96eeff 100644
> --- a/arch/riscv/kernel/head.S
> +++ b/arch/riscv/kernel/head.S
> @@ -431,6 +431,29 @@ ENTRY(reset_regs)
> csrw fcsr, 0
> /* note that the caller must clear SR_FS */
> #endif /* CONFIG_FPU */
> +
> +#ifdef CONFIG_RISCV_ISA_V
> + csrr t0, CSR_MISA
> + li t1, COMPAT_HWCAP_ISA_V
> + and t0, t0, t1
> + beqz t0, .Lreset_regs_done
> +
> + /*
> + * Clear vector registers and reset vcsr
> + * VLMAX has a defined value, VLEN is a constant,
> + * and this form of vsetvli is defined to set vl to VLMAX.
> + */
> + li t1, SR_VS
> + csrs CSR_STATUS, t1
> + csrs CSR_VCSR, x0
> + vsetvli t1, x0, e8, m8, ta, ma
> + vmv.v.i v0, 0
> + vmv.v.i v8, 0
> + vmv.v.i v16, 0
> + vmv.v.i v24, 0
> + /* note that the caller must clear SR_VS */
> +#endif /* CONFIG_RISCV_ISA_V */
> +
> .Lreset_regs_done:
> ret
> END(reset_regs)
> --
> 2.17.1
>
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next prev parent reply other threads:[~2023-01-25 21:54 UTC|newest]
Thread overview: 64+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-25 14:20 [PATCH -next v13 00/19] riscv: Add vector ISA support Andy Chiu
2023-01-25 14:20 ` [PATCH -next v13 01/19] riscv: Rename __switch_to_aux -> fpu Andy Chiu
2023-01-25 21:15 ` Conor Dooley
2023-01-25 14:20 ` [PATCH -next v13 02/19] riscv: Extending cpufeature.c to detect V-extension Andy Chiu
2023-01-25 21:33 ` Conor Dooley
2023-01-28 7:09 ` Guo Ren
2023-01-28 10:28 ` Conor Dooley
2023-01-25 14:20 ` [PATCH -next v13 03/19] riscv: Add new csr defines related to vector extension Andy Chiu
2023-01-25 22:16 ` Conor Dooley
2023-01-25 14:20 ` [PATCH -next v13 04/19] riscv: Clear vector regfile on bootup Andy Chiu
2023-01-25 21:54 ` Conor Dooley [this message]
2023-01-25 21:57 ` Vineet Gupta
2023-01-25 22:18 ` Conor Dooley
2023-01-25 14:20 ` [PATCH -next v13 05/19] riscv: Disable Vector Instructions for kernel itself Andy Chiu
2023-01-25 21:51 ` Conor Dooley
2023-01-25 14:20 ` [PATCH -next v13 06/19] riscv: Introduce Vector enable/disable helpers Andy Chiu
2023-01-26 21:06 ` Conor Dooley
2023-01-25 14:20 ` [PATCH -next v13 07/19] riscv: Introduce riscv_vsize to record size of Vector context Andy Chiu
2023-01-26 21:24 ` Conor Dooley
2023-01-25 14:20 ` [PATCH -next v13 08/19] riscv: Introduce struct/helpers to save/restore per-task Vector state Andy Chiu
2023-01-26 21:32 ` Conor Dooley
2023-01-25 14:20 ` [PATCH -next v13 09/19] riscv: Add task switch support for vector Andy Chiu
2023-01-26 21:44 ` Conor Dooley
2023-01-31 2:55 ` Vineet Gupta
2023-01-25 14:20 ` [PATCH -next v13 10/19] riscv: Allocate user's vector context in the first-use trap Andy Chiu
2023-01-26 23:11 ` Conor Dooley
2023-02-06 12:00 ` Andy Chiu
2023-02-06 13:40 ` Conor Dooley
2023-02-10 12:00 ` Andy Chiu
2023-02-07 14:36 ` Björn Töpel
2023-02-13 22:54 ` Vineet Gupta
2023-02-14 6:43 ` Björn Töpel
2023-02-14 15:36 ` Andy Chiu
2023-02-14 16:50 ` Björn Töpel
2023-02-14 17:24 ` Vineet Gupta
2023-02-15 7:14 ` Björn Töpel
2023-02-15 14:39 ` Andy Chiu
2023-02-07 21:18 ` Vineet Gupta
2023-02-08 9:20 ` Björn Töpel
2023-01-25 14:20 ` [PATCH -next v13 11/19] riscv: Add ptrace vector support Andy Chiu
2023-01-25 14:20 ` [PATCH -next v13 12/19] riscv: signal: check fp-reserved words unconditionally Andy Chiu
2023-01-25 14:20 ` [PATCH -next v13 13/19] riscv: signal: Add sigcontext save/restore for vector Andy Chiu
2023-01-25 14:20 ` [PATCH -next v13 14/19] riscv: signal: Report signal frame size to userspace via auxv Andy Chiu
2023-01-26 23:19 ` Conor Dooley
2023-01-31 12:34 ` Andy Chiu
2023-01-25 14:20 ` [PATCH -next v13 15/19] riscv: Fix a kernel panic issue if $s2 is set to a specific value before entering Linux Andy Chiu
2023-01-27 20:31 ` Conor Dooley
2023-01-31 12:34 ` Andy Chiu
2023-01-25 14:20 ` [PATCH -next v13 16/19] riscv: Add V extension to KVM ISA Andy Chiu
2023-01-27 20:43 ` Conor Dooley
2023-01-30 9:58 ` Andy Chiu
2023-01-25 14:20 ` [PATCH -next v13 17/19] riscv: KVM: Add vector lazy save/restore support Andy Chiu
2023-01-25 14:20 ` [PATCH -next v13 18/19] riscv: kvm: redirect illegal instruction traps to guests Andy Chiu
2023-01-27 11:28 ` Anup Patel
2023-01-30 8:18 ` Andy Chiu
2023-01-25 14:20 ` [PATCH -next v13 19/19] riscv: Enable Vector code to be built Andy Chiu
2023-01-25 21:04 ` Conor Dooley
2023-01-25 21:38 ` Jessica Clarke
2023-01-25 22:24 ` Conor Dooley
2023-01-30 6:38 ` Andy Chiu
2023-01-30 18:38 ` Vineet Gupta
2023-01-30 7:46 ` Andy Chiu
2023-01-30 8:13 ` Conor Dooley
2023-02-08 18:19 ` Conor Dooley
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