[kvm-unit-tests PATCH 09/14] x86: msr: Drop the explicit expected value

Sean Christopherson
2021-04-22T03:05:35Z

Use the written value as the expected value. For the vast majority of
MSRs, including all those currently tested, the expected value will
always be the last written value. This will simplify handling EFER on
32-bit vCPUs in a future patch.

Signed-off-by: Sean Christopherson <seanjc@google.com>
---
x86/msr.c | 37 +++++++++++++++++++------------------
1 file changed, 19 insertions(+), 18 deletions(-)

diff --git a/x86/msr.c b/x86/msr.c
index 0fc7978..9031043 100644
--- a/x86/msr.c
+++ b/x86/msr.c
@@ -21,42 +21,42 @@ struct msr_info {
struct msr_info msr_info[] =
{
{ .index = MSR_IA32_SYSENTER_CS, .name = "MSR_IA32_SYSENTER_CS",
- .val_pairs = {{ .valid = 1, .value = 0x1234, .expected = 0x1234}}
+ .val_pairs = {{ .valid = 1, .value = 0x1234 }}
},
{ .index = MSR_IA32_SYSENTER_ESP, .name = "MSR_IA32_SYSENTER_ESP",
- .val_pairs = {{ .valid = 1, .value = addr_ul, .expected = addr_ul}}
+ .val_pairs = {{ .valid = 1, .value = addr_ul }}
},
{ .index = MSR_IA32_SYSENTER_EIP, .name = "MSR_IA32_SYSENTER_EIP",
- .val_pairs = {{ .valid = 1, .value = addr_ul, .expected = addr_ul}}
+ .val_pairs = {{ .valid = 1, .value = addr_ul }}
},
{ .index = MSR_IA32_MISC_ENABLE, .name = "MSR_IA32_MISC_ENABLE",
// reserved: 1:2, 4:6, 8:10, 13:15, 17, 19:21, 24:33, 35:63
- .val_pairs = {{ .valid = 1, .value = 0x400c51889, .expected = 0x400c51889}}
+ .val_pairs = {{ .valid = 1, .value = 0x400c51889 }}
},
{ .index = MSR_IA32_CR_PAT, .name = "MSR_IA32_CR_PAT",
- .val_pairs = {{ .valid = 1, .value = 0x07070707, .expected = 0x07070707}}
+ .val_pairs = {{ .valid = 1, .value = 0x07070707 }}
},
#ifdef __x86_64__
{ .index = MSR_FS_BASE, .name = "MSR_FS_BASE",
- .val_pairs = {{ .valid = 1, .value = addr_64, .expected = addr_64}}
+ .val_pairs = {{ .valid = 1, .value = addr_64 }}
},
{ .index = MSR_GS_BASE, .name = "MSR_GS_BASE",
- .val_pairs = {{ .valid = 1, .value = addr_64, .expected = addr_64}}
+ .val_pairs = {{ .valid = 1, .value = addr_64 }}
},
{ .index = MSR_KERNEL_GS_BASE, .name = "MSR_KERNEL_GS_BASE",
- .val_pairs = {{ .valid = 1, .value = addr_64, .expected = addr_64}}
+ .val_pairs = {{ .valid = 1, .value = addr_64 }}
},
{ .index = MSR_EFER, .name = "MSR_EFER",
- .val_pairs = {{ .valid = 1, .value = 0xD00, .expected = 0xD00}}
+ .val_pairs = {{ .valid = 1, .value = 0xD00 }}
},
{ .index = MSR_LSTAR, .name = "MSR_LSTAR",
- .val_pairs = {{ .valid = 1, .value = addr_64, .expected = addr_64}}
+ .val_pairs = {{ .valid = 1, .value = addr_64 }}
},
{ .index = MSR_CSTAR, .name = "MSR_CSTAR",
- .val_pairs = {{ .valid = 1, .value = addr_64, .expected = addr_64}}
+ .val_pairs = {{ .valid = 1, .value = addr_64 }}
},
{ .index = MSR_SYSCALL_MASK, .name = "MSR_SYSCALL_MASK",
- .val_pairs = {{ .valid = 1, .value = 0xffffffff, .expected = 0xffffffff}}
+ .val_pairs = {{ .valid = 1, .value = 0xffffffff }}
},
#endif

@@ -75,7 +75,7 @@ static int find_msr_info(int msr_index)
return -1;
}

-static void test_msr_rw(int msr_index, unsigned long long input, unsigned long long expected)
+static void test_msr_rw(int msr_index, unsigned long long val)
{
unsigned long long r, orig;
int index;
@@ -87,16 +87,17 @@ static void test_msr_rw(int msr_index, unsigned long long input, unsigned long l
printf("couldn't find name for msr # %#x, skipping\n", msr_index);
return;
}
+
orig = rdmsr(msr_index);
- wrmsr(msr_index, input);
+ wrmsr(msr_index, val);
r = rdmsr(msr_index);
wrmsr(msr_index, orig);
- if (expected != r) {
+ if (r != val) {
printf("testing %s: output = %#" PRIx32 ":%#" PRIx32
" expected = %#" PRIx32 ":%#" PRIx32 "\n", sptr,
- (u32)(r >> 32), (u32)r, (u32)(expected >> 32), (u32)expected);
+ (u32)(r >> 32), (u32)r, (u32)(val >> 32), (u32)val);
}
- report(expected == r, "%s", sptr);
+ report(val == r, "%s", sptr);
}

int main(int ac, char **av)
@@ -105,7 +106,7 @@ int main(int ac, char **av)
for (i = 0 ; i < ARRAY_SIZE(msr_info); i++) {
for (j = 0; j < ARRAY_SIZE(msr_info[i].val_pairs); j++) {
if (msr_info[i].val_pairs[j].valid) {
- test_msr_rw(msr_info[i].index, msr_info[i].val_pairs[j].value, msr_info[i].val_pairs[j].expected);
+ test_msr_rw(msr_info[i].index, msr_info[i].val_pairs[j].value);
} else {
break;
}