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[34.83.12.150]) by smtp.gmail.com with ESMTPSA id x13sm526220pgf.13.2021.04.29.10.52.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Apr 2021 10:52:02 -0700 (PDT) Date: Thu, 29 Apr 2021 10:51:59 -0700 From: Ricardo Koller To: Marc Zyngier Cc: kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, pbonzini@redhat.com, drjones@redhat.com, alexandru.elisei@arm.com, eric.auger@redhat.com Subject: Re: [PATCH 1/3] KVM: selftests: Add exception handling support for aarch64 Message-ID: References: <20210423040351.1132218-1-ricarkol@google.com> <20210423040351.1132218-2-ricarkol@google.com> <87sg3hnzrj.wl-maz@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <87sg3hnzrj.wl-maz@kernel.org> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On Fri, Apr 23, 2021 at 09:58:24AM +0100, Marc Zyngier wrote: > Hi Ricardo, > > Thanks for starting this. > > On Fri, 23 Apr 2021 05:03:49 +0100, > Ricardo Koller wrote: > > +.pushsection ".entry.text", "ax" > > +.balign 0x800 > > +.global vectors > > +vectors: > > +.popsection > > + > > +/* > > + * Build an exception handler for vector and append a jump to it into > > + * vectors (while making sure that it's 0x80 aligned). > > + */ > > +.macro HANDLER, el, label, vector > > +handler\()\vector: > > + save_registers \el > > + mov x0, sp > > + mov x1, \vector > > + bl route_exception > > + restore_registers \el > > + > > +.pushsection ".entry.text", "ax" > > +.balign 0x80 > > + b handler\()\vector > > +.popsection > > +.endm > > That's an interesting construct, wildly different from what we are > using elsewhere in the kernel, but hey, I like change ;-). It'd be > good to add a comment to spell out that anything that emits into > .entry.text between the declaration of 'vectors' and the end of this > file will break everything. > > > + > > +.global ex_handler_code > > +ex_handler_code: > > + HANDLER 1, sync, 0 // Synchronous EL1t > > + HANDLER 1, irq, 1 // IRQ EL1t > > + HANDLER 1, fiq, 2 // FIQ EL1t > > + HANDLER 1, error, 3 // Error EL1t > > Can any of these actually happen? As far as I can see, the whole > selftest environment seems to be designed around EL1h. > They can happen. KVM defaults to use EL1h: #define VCPU_RESET_PSTATE_EL1 (PSR_MODE_EL1h | PSR_A_BIT | PSR_I_BIT | \ but then a guest can set the SPSel to 0: asm volatile("msr spsel, #0"); and this happens: Unexpected exception guest (vector:0x0, ec:0x25) I think it should still be a valid situation: some test might want to try it. Thanks, Ricardo